diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 100 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 77 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 51 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SystemOperands.td | 83 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 41 |
6 files changed, 297 insertions, 72 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index a16e8a1bd16..f91473509b0 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -65,6 +65,18 @@ def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; +def FeaturePAN : SubtargetFeature< + "pan", "HasPAN", "true", + "Enables ARM v8.1 Privileged Access-Never extension">; + +def FeatureLOR : SubtargetFeature< + "lor", "HasLOR", "true", + "Enables ARM v8.1 Limited Ordering Regions extension">; + +def FeatureVH : SubtargetFeature< + "vh", "HasVH", "true", + "Enables ARM v8.1 Virtual Host extension">; + def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", "Enable ARMv8 PMUv3 Performance Monitors extension">; @@ -77,6 +89,18 @@ def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", "Enable Statistical Profiling extension">; +def FeaturePAN_RWV : SubtargetFeature< + "pan-rwv", "HasPAN_RWV", "true", + "Enable v8.2 PAN s1e1R and s1e1W Variants", + [FeaturePAN]>; + +// UAO PState +def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", + "Enable v8.2 UAO PState">; + +def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", + "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; + def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", "Enable Scalable Vector Extension (SVE) instructions">; @@ -195,6 +219,66 @@ def FeatureDotProd : SubtargetFeature< "dotprod", "HasDotProd", "true", "Enable dot product support">; +def FeaturePA : SubtargetFeature< + "pa", "HasPA", "true", + "Enable v8.3-A Pointer Authentication enchancement">; + +def FeatureJS : SubtargetFeature< + "jsconv", "HasJS", "true", + "Enable v8.3-A JavaScript FP conversion enchancement", + [FeatureFPARMv8]>; + +def FeatureCCIDX : SubtargetFeature< + "ccidx", "HasCCIDX", "true", + "Enable v8.3-A Extend of the CCSIDR number of sets">; + +def FeatureComplxNum : SubtargetFeature< + "complxnum", "HasComplxNum", "true", + "Enable v8.3-A Floating-point complex number support", + [FeatureNEON]>; + +def FeatureNV : SubtargetFeature< + "nv", "HasNV", "true", + "Enable v8.4-A Nested Virtualization Enchancement">; + +def FeatureRASv8_4 : SubtargetFeature< + "rasv8_4", "HasRASv8_4", "true", + "Enable v8.4-A Reliability, Availability and Serviceability extension", + [FeatureRAS]>; + +def FeatureMPAM : SubtargetFeature< + "mpam", "HasMPAM", "true", + "Enable v8.4-A Memory system Partitioning and Monitoring extension">; + +def FeatureDIT : SubtargetFeature< + "dit", "HasDIT", "true", + "Enable v8.4-A Data Independent Timing instructions">; + +def FeatureTRACEV8_4 : SubtargetFeature< + "tracev8.4", "HasTRACEV8_4", "true", + "Enable v8.4-A Trace extension">; + +def FeatureAM : SubtargetFeature< + "am", "HasAM", "true", + "Enable v8.4-A Activity Monitors extension">; + +def FeatureSEL2 : SubtargetFeature< + "sel2", "HasSEL2", "true", + "Enable v8.4-A Secure Exception Level 2 extension">; + +def FeatureTLB_RMI : SubtargetFeature< + "tlb-rmi", "HasTLB_RMI", "true", + "Enable v8.4-A TLB Range and Maintenance Instructions">; + +def FeatureFMI : SubtargetFeature< + "fmi", "HasFMI", "true", + "Enable v8.4-A Flag Manipulation Instructions">; + +// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset +def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", + "Enable v8.4-A RCPC instructions with Immediate Offsets", + [FeatureRCPC]>; + def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", "NegativeImmediates", "false", "Convert immediates and instructions " @@ -232,7 +316,7 @@ def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true", "Enable execution and data prediction invalidation instructions" >; def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", - "true", "Enable Cache Clean to Point of Deep Persistence" >; + "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", "true", "Enable Branch Target Identification" >; @@ -248,16 +332,22 @@ def FeatureMTE : SubtargetFeature<"mte", "HasMTE", // def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", - "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>; + "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, + FeaturePAN, FeatureLOR, FeatureVH]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", - "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>; + "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, + FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", - "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>; + "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, + FeatureJS, FeatureCCIDX, FeatureComplxNum]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", - "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; + "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, + FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT, + FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI, + FeatureFMI, FeatureRCPC_IMMO]>; def HasV8_5aOps : SubtargetFeature< "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index ab90ea3f74a..9061ed4f9f5 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -9989,9 +9989,10 @@ class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode, let Inst{4-0} = Rd; } +//8.3 CompNum - Floating-point complex number support multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, string asm, SDPatternOperator OpNode>{ - let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), @@ -10007,7 +10008,7 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, (rottype i32:$rot)))]>; } - let Predicates = [HasV8_3a, HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), @@ -10063,7 +10064,7 @@ class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size, multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, Operand rottype, string asm, SDPatternOperator OpNode> { - let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), @@ -10079,7 +10080,7 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, (rottype i32:$rot)))]>; } - let Predicates = [HasV8_3a, HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), @@ -10145,7 +10146,7 @@ class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size, // classes. multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, string asm, SDPatternOperator OpNode> { - let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64, V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h", ".4h", ".h", []> { @@ -10161,9 +10162,9 @@ multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, let Inst{11} = idx{1}; let Inst{21} = idx{0}; } - } // Predicates = [HasV8_3a,HasNEON,HasFullFP16] + } // Predicates = HasComplxNum, HasNEON, HasFullFP16] - let Predicates = [HasV8_3a,HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2, V128, V128, V128, VectorIndexD, rottype, asm, ".4s", ".4s", ".4s", ".s", []> { @@ -10171,7 +10172,7 @@ multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, let Inst{11} = idx{0}; let Inst{21} = 0; } - } // Predicates = [HasV8_3a,HasNEON] + } // Predicates = [HasComplxNum, HasNEON] } //---------------------------------------------------------------------------- diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index cfe05822fd2..ee43b55aed9 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -24,6 +24,54 @@ def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; +def HasVH : Predicate<"Subtarget->hasVH()">, + AssemblerPredicate<"FeatureVH", "vh">; + +def HasLOR : Predicate<"Subtarget->hasLOR()">, + AssemblerPredicate<"FeatureLOR", "lor">; + +def HasPA : Predicate<"Subtarget->hasPA()">, + AssemblerPredicate<"FeaturePA", "pa">; + +def HasJS : Predicate<"Subtarget->hasJS()">, + AssemblerPredicate<"FeatureJS", "jsconv">; + +def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">, + AssemblerPredicate<"FeatureCCIDX", "ccidx">; + +def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">, + AssemblerPredicate<"FeatureComplxNum", "complxnum">; + +def HasNV : Predicate<"Subtarget->hasNV()">, + AssemblerPredicate<"FeatureNV", "nv">; + +def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">, + AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">; + +def HasMPAM : Predicate<"Subtarget->hasMPAM()">, + AssemblerPredicate<"FeatureMPAM", "mpam">; + +def HasDIT : Predicate<"Subtarget->hasDIT()">, + AssemblerPredicate<"FeatureDIT", "dit">; + +def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">, + AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">; + +def HasAM : Predicate<"Subtarget->hasAM()">, + AssemblerPredicate<"FeatureAM", "am">; + +def HasSEL2 : Predicate<"Subtarget->hasSEL2()">, + AssemblerPredicate<"FeatureSEL2", "sel2">; + +def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">, + AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">; + +def HasFMI : Predicate<"Subtarget->hasFMI()">, + AssemblerPredicate<"FeatureFMI", "fmi">; + +def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">, + AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">; + def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, @@ -510,7 +558,7 @@ def ISB : CRmSystemI<barrier_op, 0b110, "isb", def TSB : CRmSystemI<barrier_op, 0b010, "tsb", []> { let CRm = 0b0010; let Inst{12} = 0; - let Predicates = [HasV8_4a]; + let Predicates = [HasTRACEV8_4]; } } @@ -602,7 +650,7 @@ let Uses = [LR], Defs = [LR], CRm = 0b0000 in { } // These pointer authentication isntructions require armv8.3a -let Predicates = [HasV8_3a] in { +let Predicates = [HasPA] in { multiclass SignAuth<bits<3> prefix, bits<3> prefix_z, string asm> { def IA : SignAuthOneData<prefix, 0b00, !strconcat(asm, "ia")>; def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib")>; @@ -642,17 +690,17 @@ let Predicates = [HasV8_3a] in { defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; - // v8.3a floating point conversion for javascript - let Predicates = [HasV8_3a, HasFPARMv8] in - def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, - "fjcvtzs", []> { - let Inst{31} = 0; - } +} -} // HasV8_3a +// v8.3a floating point conversion for javascript +let Predicates = [HasJS, HasFPARMv8] in +def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, + "fjcvtzs", []> { + let Inst{31} = 0; +} // HasJS, HasFPARMv8 // v8.4 Flag manipulation instructions -let Predicates = [HasV8_4a] in { +let Predicates = [HasFMI] in { def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> { let Inst{20-5} = 0b0000001000000000; } @@ -660,7 +708,7 @@ def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">; def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">; def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif", "{\t$Rn, $imm, $mask}">; -} // HasV8_4a +} // HasFMI // v8.5 flag manipulation instructions let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in { @@ -2629,8 +2677,9 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", [(truncstorei8 GPR32z:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; -// Armv8.4 LDAPR & STLR with Immediate Offset instruction -let Predicates = [HasV8_4a] in { +// Armv8.4 Weaker Release Consistency enhancements +// LDAPR & STLR with Immediate Offset instructions +let Predicates = [HasRCPC_IMMO] in { defm STLURB : BaseStoreUnscaleV84<"stlurb", 0b00, 0b00, GPR32>; defm STLURH : BaseStoreUnscaleV84<"stlurh", 0b01, 0b00, GPR32>; defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>; @@ -2915,7 +2964,7 @@ def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">; def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">; def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">; -let Predicates = [HasV8_1a] in { +let Predicates = [HasLOR] in { // v8.1a "Limited Order Region" extension load-acquire instructions def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">; def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index db3432bc646..9b27e0a0e8f 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -83,6 +83,33 @@ protected: bool HasFP16FML = false; bool HasSPE = false; + // ARMv8.1 extensions + bool HasVH = false; + bool HasPAN = false; + bool HasLOR = false; + + // ARMv8.2 extensions + bool HasPsUAO = false; + bool HasPAN_RWV = false; + bool HasCCPP = false; + + // ARMv8.3 extensions + bool HasPA = false; + bool HasJS = false; + bool HasCCIDX = false; + bool HasComplxNum = false; + + // ARMv8.4 extensions + bool HasNV = false; + bool HasRASv8_4 = false; + bool HasMPAM = false; + bool HasDIT = false; + bool HasTRACEV8_4 = false; + bool HasAM = false; + bool HasSEL2 = false; + bool HasTLB_RMI = false; + bool HasFMI = false; + bool HasRCPC_IMMO = false; // ARMv8.4 Crypto extensions bool HasSM4 = true; bool HasSHA3 = true; @@ -351,6 +378,30 @@ public: bool useAA() const override { return UseAA; } + bool hasVH() const { return HasVH; } + bool hasPAN() const { return HasPAN; } + bool hasLOR() const { return HasLOR; } + + bool hasPsUAO() const { return HasPsUAO; } + bool hasPAN_RWV() const { return HasPAN_RWV; } + bool hasCCPP() const { return HasCCPP; } + + bool hasPA() const { return HasPA; } + bool hasJS() const { return HasJS; } + bool hasCCIDX() const { return HasCCIDX; } + bool hasComplxNum() const { return HasComplxNum; } + + bool hasNV() const { return HasNV; } + bool hasRASv8_4() const { return HasRASv8_4; } + bool hasMPAM() const { return HasMPAM; } + bool hasDIT() const { return HasDIT; } + bool hasTRACEV8_4() const { return HasTRACEV8_4; } + bool hasAM() const { return HasAM; } + bool hasSEL2() const { return HasSEL2; } + bool hasTLB_RMI() const { return HasTLB_RMI; } + bool hasFMI() const { return HasFMI; } + bool hasRCPC_IMMO() const { return HasRCPC_IMMO; } + bool useSmallAddressing() const { switch (TLInfo.getTargetMachine().getCodeModel()) { case CodeModel::Kernel: diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index 7e56f426a2e..60d48e4d99d 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -15,6 +15,25 @@ include "llvm/TableGen/SearchableTable.td" //===----------------------------------------------------------------------===// +// Features that, for the compiler, only enable system operands and PStates +//===----------------------------------------------------------------------===// + +def HasCCPP : Predicate<"Subtarget->hasCCPP()">, + AssemblerPredicate<"FeatureCCPP", "ccpp">; + +def HasPAN : Predicate<"Subtarget->hasPAN()">, + AssemblerPredicate<"FeaturePAN", + "ARM v8.1 Privileged Access-Never extension">; + +def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, + AssemblerPredicate<"FeaturePsUAO", + "ARM v8.2 UAO PState extension (psuao)">; + +def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, + AssemblerPredicate<"FeaturePAN_RWV", + "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; + +//===----------------------------------------------------------------------===// // AT (address translate) instruction options. //===----------------------------------------------------------------------===// @@ -45,7 +64,7 @@ def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>; def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>; def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>; -let Requires = [{ {AArch64::HasV8_2aOps} }] in { +let Requires = [{ {AArch64::FeaturePAN_RWV} }] in { def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>; def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>; } @@ -102,7 +121,7 @@ def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>; def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; -let Requires = [{ {AArch64::HasV8_2aOps} }] in +let Requires = [{ {AArch64::FeatureCCPP} }] in def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in @@ -178,7 +197,7 @@ class TSB<string name, bits<4> encoding> : SearchableTable{ bits<4> Encoding; let Encoding = encoding; - code Requires = [{ {AArch64::HasV8_4aOps} }]; + code Requires = [{ {AArch64::FeatureTRACEV8_4} }]; } def : TSB<"csync", 0>; @@ -314,13 +333,14 @@ def : PState<"SPSel", 0b00101>; def : PState<"DAIFSet", 0b11110>; def : PState<"DAIFClr", 0b11111>; // v8.1a "Privileged Access Never" extension-specific PStates -let Requires = [{ {AArch64::HasV8_1aOps} }] in +let Requires = [{ {AArch64::FeaturePAN} }] in def : PState<"PAN", 0b00100>; + // v8.2a "User Access Override" extension-specific PStates -let Requires = [{ {AArch64::HasV8_2aOps} }] in +let Requires = [{ {AArch64::FeaturePsUAO} }] in def : PState<"UAO", 0b00011>; // v8.4a timining insensitivity of data processing instructions -let Requires = [{ {AArch64::HasV8_4aOps} }] in +let Requires = [{ {AArch64::FeatureDIT} }] in def : PState<"DIT", 0b11010>; // v8.5a Spectre Mitigation let Requires = [{ {AArch64::FeatureSSBS} }] in @@ -413,8 +433,9 @@ def : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>; def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; +// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI) +let Requires = [{ {AArch64::FeatureTLB_RMI} }] in { // Armv8.4-A Outer Sharable TLB Maintenance instructions: -let Requires = [{ {AArch64::HasV8_4aOps} }] in { // op1 CRn CRm op2 def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; @@ -465,7 +486,7 @@ def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; -} +} //FeatureTLB_RMI // Armv8.5-A Prediction Restriction by Context instruction options: class PRCTX<string name, bits<4> crm> : SearchableTable { @@ -540,8 +561,10 @@ def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>; def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>; def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>; def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>; + +//v8.3 CCIDX - extending the CCsIDr number of sets def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> { - let Requires = [{ {AArch64::HasV8_3aOps} }]; + let Requires = [{ {AArch64::FeatureCCIDX} }]; } def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>; def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>; @@ -579,9 +602,7 @@ def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>; def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>; def : ROSysReg<"ID_AA64MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b000>; def : ROSysReg<"ID_AA64MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b001>; -def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> { - let Requires = [{ {AArch64::HasV8_2aOps} }]; -} +def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010>; def : ROSysReg<"MVFR0_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b000>; def : ROSysReg<"MVFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b001>; def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>; @@ -651,7 +672,7 @@ def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; // v8.1a "Limited Ordering Regions" extension-specific system register // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::HasV8_1aOps} }] in +let Requires = [{ {AArch64::FeatureLOR} }] in def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>; // v8.2a "RAS extension" registers @@ -1185,21 +1206,21 @@ def : RWSysReg<"ICH_LR14_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b110>; def : RWSysReg<"ICH_LR15_EL2", 0b11, 0b100, 0b1100, 0b1101, 0b111>; // v8.1a "Privileged Access Never" extension-specific system registers -let Requires = [{ {AArch64::HasV8_1aOps} }] in +let Requires = [{ {AArch64::FeaturePAN} }] in def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>; // v8.1a "Limited Ordering Regions" extension-specific system registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::HasV8_1aOps} }] in { +let Requires = [{ {AArch64::FeatureLOR} }] in { def : RWSysReg<"LORSA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b000>; def : RWSysReg<"LOREA_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b001>; def : RWSysReg<"LORN_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b010>; def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>; } -// v8.1a "Virtualization hos extensions" system registers +// v8.1a "Virtualization Host extensions" system registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::HasV8_1aOps} }] in { +let Requires = [{ {AArch64::FeatureVH} }] in { def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>; def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>; def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>; @@ -1230,7 +1251,7 @@ def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>; } // v8.2a registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::HasV8_2aOps} }] in +let Requires = [{ {AArch64::FeaturePsUAO} }] in def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>; // v8.2a "Statistical Profiling extension" registers @@ -1267,7 +1288,7 @@ def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; // v8.3a "Pointer authentication extension" registers // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::HasV8_3aOps} }] in { +let Requires = [{ {AArch64::FeaturePA} }] in { def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; @@ -1280,8 +1301,8 @@ def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; } -let Requires = [{ {AArch64::HasV8_4aOps} }] in { - +// v8.4 "Secure Exception Level 2 extension" +let Requires = [{ {AArch64::FeatureSEL2} }] in { // v8.4a "Virtualization secure second stage translation" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; @@ -1299,18 +1320,22 @@ def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; // v8.4a "Virtualization debug state" registers // Op0 Op1 CRn CRm Op2 def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; +} // FeatureSEL2 // v8.4a RAS registers -// Op0 Op1 CRn CRm Op2 +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureRASv8_4} }] in { def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>; def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; +} // FeatureRASv8_4 // v8.4a MPAM registers // Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureMPAM} }] in { def : RWSysReg<"MPAM0_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b001>; def : RWSysReg<"MPAM1_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b000>; def : RWSysReg<"MPAM2_EL2", 0b11, 0b100, 0b1010, 0b0101, 0b000>; @@ -1327,9 +1352,11 @@ def : RWSysReg<"MPAMVPM5_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b101>; def : RWSysReg<"MPAMVPM6_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b110>; def : RWSysReg<"MPAMVPM7_EL2", 0b11, 0b100, 0b1010, 0b0110, 0b111>; def : ROSysReg<"MPAMIDR_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b100>; +} //FeatureMPAM -// v8.4a Activitiy monitor registers +// v8.4a Activitiy Monitor registers // Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureAM} }] in { def : RWSysReg<"AMCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b000>; def : ROSysReg<"AMCFGR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b001>; def : ROSysReg<"AMCGCR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b010>; @@ -1378,6 +1405,7 @@ def : RWSysReg<"AMEVTYPER112_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b100>; def : RWSysReg<"AMEVTYPER113_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b101>; def : RWSysReg<"AMEVTYPER114_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b110>; def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; +} //FeatureAM // v8.4a Trace Extension registers // @@ -1386,19 +1414,24 @@ def : RWSysReg<"AMEVTYPER115_EL0", 0b11, 0b011, 0b1101, 0b1111, 0b111>; // but they are already defined above. // // Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureTRACEV8_4} }] in { def : RWSysReg<"TRFCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b001>; def : RWSysReg<"TRFCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b001>; def : RWSysReg<"TRFCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b001>; +} //FeatureTRACEV8_4 // v8.4a Timining insensitivity of data processing instructions +// DIT: Data Independent Timing instructions // Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureDIT} }] in { def : RWSysReg<"DIT", 0b11, 0b011, 0b0100, 0b0010, 0b101>; +} //FeatureDIT // v8.4a Enhanced Support for Nested Virtualization // Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureNV} }] in { def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; - -} // HasV8_4aOps +} //FeatureNV // SVE control registers // Op0 Op1 CRn CRm Op2 diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 0f291cb8382..2c78818963c 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2813,28 +2813,29 @@ static const struct Extension { const char *Name; const FeatureBitset Features; } ExtensionMap[] = { - { "crc", {AArch64::FeatureCRC} }, - { "sm4", {AArch64::FeatureSM4} }, - { "sha3", {AArch64::FeatureSHA3} }, - { "sha2", {AArch64::FeatureSHA2} }, - { "aes", {AArch64::FeatureAES} }, - { "crypto", {AArch64::FeatureCrypto} }, - { "fp", {AArch64::FeatureFPARMv8} }, - { "simd", {AArch64::FeatureNEON} }, - { "ras", {AArch64::FeatureRAS} }, - { "lse", {AArch64::FeatureLSE} }, - { "predctrl", {AArch64::FeaturePredCtrl} }, - { "ccdp", {AArch64::FeatureCacheDeepPersist} }, - { "mte", {AArch64::FeatureMTE} }, - - // FIXME: Unsupported extensions - { "pan", {} }, - { "lor", {} }, - { "rdma", {} }, - { "profile", {} }, + {"crc", {AArch64::FeatureCRC}}, + {"sm4", {AArch64::FeatureSM4}}, + {"sha3", {AArch64::FeatureSHA3}}, + {"sha2", {AArch64::FeatureSHA2}}, + {"aes", {AArch64::FeatureAES}}, + {"crypto", {AArch64::FeatureCrypto}}, + {"fp", {AArch64::FeatureFPARMv8}}, + {"simd", {AArch64::FeatureNEON}}, + {"ras", {AArch64::FeatureRAS}}, + {"lse", {AArch64::FeatureLSE}}, + {"predctrl", {AArch64::FeaturePredCtrl}}, + {"ccdp", {AArch64::FeatureCacheDeepPersist}}, + {"mte", {AArch64::FeatureMTE}}, + {"tlb-rmi", {AArch64::FeatureTLB_RMI}}, + {"pan-rwv", {AArch64::FeaturePAN_RWV}}, + {"ccpp", {AArch64::FeatureCCPP}}, + // FIXME: Unsupported extensions + {"pan", {}}, + {"lor", {}}, + {"rdma", {}}, + {"profile", {}}, }; - static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) { if (FBS[AArch64::HasV8_1aOps]) Str += "ARMv8.1a"; |
