diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index ab90ea3f74a..9061ed4f9f5 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -9989,9 +9989,10 @@ class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode, let Inst{4-0} = Rd; } +//8.3 CompNum - Floating-point complex number support multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, string asm, SDPatternOperator OpNode>{ - let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), @@ -10007,7 +10008,7 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype, (rottype i32:$rot)))]>; } - let Predicates = [HasV8_3a, HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), @@ -10063,7 +10064,7 @@ class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size, multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, Operand rottype, string asm, SDPatternOperator OpNode> { - let Predicates = [HasV8_3a, HasNEON, HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64, rottype, asm, ".4h", [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd), @@ -10079,7 +10080,7 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode, (rottype i32:$rot)))]>; } - let Predicates = [HasV8_3a, HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v2f32 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b10, opcode, V64, rottype, asm, ".2s", [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd), @@ -10145,7 +10146,7 @@ class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size, // classes. multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, string asm, SDPatternOperator OpNode> { - let Predicates = [HasV8_3a,HasNEON,HasFullFP16] in { + let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in { def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64, V64, V128, VectorIndexD, rottype, asm, ".4h", ".4h", ".4h", ".h", []> { @@ -10161,9 +10162,9 @@ multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, let Inst{11} = idx{1}; let Inst{21} = idx{0}; } - } // Predicates = [HasV8_3a,HasNEON,HasFullFP16] + } // Predicates = HasComplxNum, HasNEON, HasFullFP16] - let Predicates = [HasV8_3a,HasNEON] in { + let Predicates = [HasComplxNum, HasNEON] in { def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2, V128, V128, V128, VectorIndexD, rottype, asm, ".4s", ".4s", ".4s", ".s", []> { @@ -10171,7 +10172,7 @@ multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype, let Inst{11} = idx{0}; let Inst{21} = 0; } - } // Predicates = [HasV8_3a,HasNEON] + } // Predicates = [HasComplxNum, HasNEON] } //---------------------------------------------------------------------------- |
