AArch64: TableGenerate system instruction operands.

The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

llvm-svn: 274576

2 files changed, 16 insertions, 16 deletions

diff --git a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
index 9027a60dd30..e31d3232951 100644
--- a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
+++ b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
@@ -48,7 +48,7 @@
 # CHECK: sys #2, c0, c5, #7
 # CHECK: sys #7, c6, c10, #7, x7
 # CHECK: sysl  x20, #6, c3, c15, #7
-# CHECK: msr  SPSEL, #0
+# CHECK: msr  SPSel, #0
 # CHECK: msr S3_0_C11_C0_0, x0
 # CHECK: mrs x0, S3_0_C11_C0_0
 
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 9d6723a96e4..4d438e032e7 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3131,9 +3131,9 @@
 0xdf 0x3f 0x3 0xd5
 0xdf 0x3c 0x3 0xd5
 
-# CHECK: msr      {{spsel|SPSEL}}, #0
-# CHECK: msr      {{daifset|DAIFSET}}, #15
-# CHECK: msr      {{daifclr|DAIFCLR}}, #12
+# CHECK: msr      {{SPSel|SPSEL}}, #0
+# CHECK: msr      {{DAIFSet|DAIFSET}}, #15
+# CHECK: msr      {{DAIFClr|DAIFCLR}}, #12
 0xbf 0x40 0x0 0xd5
 0xdf 0x4f 0x3 0xd5
 0xff 0x4c 0x3 0xd5
@@ -3289,14 +3289,14 @@
 # CHECK: msr      {{sp_el0|SP_EL0}}, x12
 # CHECK: msr      {{sp_el1|SP_EL1}}, x12
 # CHECK: msr      {{sp_el2|SP_EL2}}, x12
-# CHECK: msr      {{spsel|SPSEL}}, x12
+# CHECK: msr      {{SPSel|SPSEL}}, x12
 # CHECK: msr      {{nzcv|NZCV}}, x12
 # CHECK: msr      {{daif|DAIF}}, x12
-# CHECK: msr      {{currentel|CURRENTEL}}, x12
-# CHECK: msr      {{spsr_irq|SPSR_IRQ}}, x12
-# CHECK: msr      {{spsr_abt|SPSR_ABT}}, x12
-# CHECK: msr      {{spsr_und|SPSR_UND}}, x12
-# CHECK: msr      {{spsr_fiq|SPSR_FIQ}}, x12
+# CHECK: msr      {{CurrentEL|CURRENTEL}}, x12
+# CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12
+# CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12
+# CHECK: msr      {{SPSR_und|SPSR_UND}}, x12
+# CHECK: msr      {{SPSR_fiq|SPSR_FIQ}}, x12
 # CHECK: msr      {{fpcr|FPCR}}, x12
 # CHECK: msr      {{fpsr|FPSR}}, x12
 # CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12
@@ -3581,14 +3581,14 @@
 # CHECK: mrs      x9, {{sp_el0|SP_EL0}}
 # CHECK: mrs      x9, {{sp_el1|SP_EL1}}
 # CHECK: mrs      x9, {{sp_el2|SP_EL2}}
-# CHECK: mrs      x9, {{spsel|SPSEL}}
+# CHECK: mrs      x9, {{SPSel|SPSEL}}
 # CHECK: mrs      x9, {{nzcv|NZCV}}
 # CHECK: mrs      x9, {{daif|DAIF}}
-# CHECK: mrs      x9, {{currentel|CURRENTEL}}
-# CHECK: mrs      x9, {{spsr_irq|SPSR_IRQ}}
-# CHECK: mrs      x9, {{spsr_abt|SPSR_ABT}}
-# CHECK: mrs      x9, {{spsr_und|SPSR_UND}}
-# CHECK: mrs      x9, {{spsr_fiq|SPSR_FIQ}}
+# CHECK: mrs      x9, {{CurrentEL|CURRENTEL}}
+# CHECK: mrs      x9, {{SPSR_irq|SPSR_IRQ}}
+# CHECK: mrs      x9, {{SPSR_abt|SPSR_ABT}}
+# CHECK: mrs      x9, {{SPSR_und|SPSR_UND}}
+# CHECK: mrs      x9, {{SPSR_fiq|SPSR_FIQ}}
 # CHECK: mrs      x9, {{fpcr|FPCR}}
 # CHECK: mrs      x9, {{fpsr|FPSR}}
 # CHECK: mrs      x9, {{dspsr_el0|DSPSR_EL0}}