AArch64: TableGenerate system instruction operands.

The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

llvm-svn: 274576

6 files changed, 39 insertions, 39 deletions

diff --git a/llvm/test/CodeGen/AArch64/special-reg.ll b/llvm/test/CodeGen/AArch64/special-reg.ll
index 91c32158d42..4b8c75b7098 100644
--- a/llvm/test/CodeGen/AArch64/special-reg.ll
+++ b/llvm/test/CodeGen/AArch64/special-reg.ll
@@ -35,7 +35,7 @@ entry:
 define void @write_daifset() nounwind {
 entry:
 ; CHECK-LABEL: write_daifset:
-; CHECK: msr DAIFSET, #2
+; CHECK: msr DAIFSet, #2
   call void @llvm.write_register.i64(metadata !2, i64 2)
   ret void
 }
diff --git a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
index f1d94d8c2d8..f1c675f6edf 100644
--- a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
+++ b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
@@ -8,11 +8,11 @@ msr ESR_EL1, x0
 mrs x0, SPSel
 mrs x0, ESR_EL1
 
-// CHECK: msr SPSEL, #0               // encoding: [0xbf,0x40,0x00,0xd5]
-// CHECK: msr SPSEL, x0               // encoding: [0x00,0x42,0x18,0xd5]
-// CHECK: msr DAIFSET, #0             // encoding: [0xdf,0x40,0x03,0xd5]
+// CHECK: msr SPSel, #0               // encoding: [0xbf,0x40,0x00,0xd5]
+// CHECK: msr SPSel, x0               // encoding: [0x00,0x42,0x18,0xd5]
+// CHECK: msr DAIFSet, #0             // encoding: [0xdf,0x40,0x03,0xd5]
 // CHECK: msr ESR_EL1, x0             // encoding: [0x00,0x52,0x18,0xd5]
-// CHECK: mrs x0, SPSEL               // encoding: [0x00,0x42,0x38,0xd5]
+// CHECK: mrs x0, SPSel               // encoding: [0x00,0x42,0x38,0xd5]
 // CHECK: mrs x0, ESR_EL1             // encoding: [0x00,0x52,0x38,0xd5]
 
 
diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s
index eb29117428f..ef4037b7bf3 100644
--- a/llvm/test/MC/AArch64/arm64-system-encoding.s
+++ b/llvm/test/MC/AArch64/arm64-system-encoding.s
@@ -167,7 +167,7 @@ foo:
 ; CHECK: msr CPTR_EL2, x3               ; encoding: [0x43,0x11,0x1c,0xd5]
 ; CHECK: msr CPTR_EL3, x3               ; encoding: [0x43,0x11,0x1e,0xd5]
 ; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CURRENTEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
+; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
 ; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]
 ; CHECK: msr ESR_EL1, x3                ; encoding: [0x03,0x52,0x18,0xd5]
 ; CHECK: msr ESR_EL2, x3                ; encoding: [0x03,0x52,0x1c,0xd5]
@@ -213,7 +213,7 @@ foo:
 ; CHECK: msr VPIDR_EL2, x3              ; encoding: [0x03,0x00,0x1c,0xd5]
 ; CHECK: msr VTCR_EL2, x3               ; encoding: [0x43,0x21,0x1c,0xd5]
 ; CHECK: msr VTTBR_EL2, x3              ; encoding: [0x03,0x21,0x1c,0xd5]
-; CHECK: msr  SPSEL, x3                 ; encoding: [0x03,0x42,0x18,0xd5]
+; CHECK: msr  SPSel, x3                 ; encoding: [0x03,0x42,0x18,0xd5]
 ; CHECK: msr  S3_2_C11_C6_4, x1         ; encoding: [0x81,0xb6,0x1a,0xd5]
 ; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]
 ; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]
@@ -439,7 +439,7 @@ foo:
 ; CHECK: mrs x3, CPTR_EL3               ; encoding: [0x43,0x11,0x3e,0xd5]
 ; CHECK: mrs x3, CSSELR_EL1             ; encoding: [0x03,0x00,0x3a,0xd5]
 ; CHECK: mrs x3, CTR_EL0                ; encoding: [0x23,0x00,0x3b,0xd5]
-; CHECK: mrs x3, CURRENTEL              ; encoding: [0x43,0x42,0x38,0xd5]
+; CHECK: mrs x3, CurrentEL              ; encoding: [0x43,0x42,0x38,0xd5]
 ; CHECK: mrs x3, DACR32_EL2             ; encoding: [0x03,0x30,0x3c,0xd5]
 ; CHECK: mrs x3, DCZID_EL0              ; encoding: [0xe3,0x00,0x3b,0xd5]
 ; CHECK: mrs x3, REVIDR_EL1             ; encoding: [0xc3,0x00,0x38,0xd5]
diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s
index 69229848fde..8a82c99eb8c 100644
--- a/llvm/test/MC/AArch64/basic-a64-instructions.s
+++ b/llvm/test/MC/AArch64/basic-a64-instructions.s
@@ -3571,9 +3571,9 @@ _func:
         msr spsel, #0
         msr daifset, #15
         msr daifclr, #12
-// CHECK: msr     {{spsel|SPSEL}}, #0               // encoding: [0xbf,0x40,0x00,0xd5]
-// CHECK: msr     {{daifset|DAIFSET}}, #15            // encoding: [0xdf,0x4f,0x03,0xd5]
-// CHECK: msr     {{daifclr|DAIFCLR}}, #12            // encoding: [0xff,0x4c,0x03,0xd5]
+// CHECK: msr     {{SPSel|SPSEL}}, #0               // encoding: [0xbf,0x40,0x00,0xd5]
+// CHECK: msr     {{DAIFSet|DAIFSET}}, #15            // encoding: [0xdf,0x4f,0x03,0xd5]
+// CHECK: msr     {{DAIFClr|DAIFCLR}}, #12            // encoding: [0xff,0x4c,0x03,0xd5]
 
         sys #7, c5, c9, #7, x5
         sys #0, c15, c15, #2
@@ -4070,14 +4070,14 @@ _func:
 // CHECK: msr      {{sp_el0|SP_EL0}}, x12                // encoding: [0x0c,0x41,0x18,0xd5]
 // CHECK: msr      {{sp_el1|SP_EL1}}, x12                // encoding: [0x0c,0x41,0x1c,0xd5]
 // CHECK: msr      {{sp_el2|SP_EL2}}, x12                // encoding: [0x0c,0x41,0x1e,0xd5]
-// CHECK: msr      {{spsel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
+// CHECK: msr      {{SPSel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
 // CHECK: msr      {{nzcv|NZCV}}, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]
 // CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
-// CHECK: msr      {{currentel|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
-// CHECK: msr      {{spsr_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
-// CHECK: msr      {{spsr_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
-// CHECK: msr      {{spsr_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
-// CHECK: msr      {{spsr_fiq|SPSR_FIQ}}, x12              // encoding: [0x6c,0x43,0x1c,0xd5]
+// CHECK: msr      {{CurrentEL|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
+// CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
+// CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
+// CHECK: msr      {{SPSR_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
+// CHECK: msr      {{SPSR_fiq|SPSR_FIQ}}, x12              // encoding: [0x6c,0x43,0x1c,0xd5]
 // CHECK: msr      {{fpcr|FPCR}}, x12                  // encoding: [0x0c,0x44,0x1b,0xd5]
 // CHECK: msr      {{fpsr|FPSR}}, x12                  // encoding: [0x2c,0x44,0x1b,0xd5]
 // CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12             // encoding: [0x0c,0x45,0x1b,0xd5]
@@ -4665,14 +4665,14 @@ _func:
 // CHECK: mrs      x9, {{sp_el0|SP_EL0}}                 // encoding: [0x09,0x41,0x38,0xd5]
 // CHECK: mrs      x9, {{sp_el1|SP_EL1}}                 // encoding: [0x09,0x41,0x3c,0xd5]
 // CHECK: mrs      x9, {{sp_el2|SP_EL2}}                 // encoding: [0x09,0x41,0x3e,0xd5]
-// CHECK: mrs      x9, {{spsel|SPSEL}}                  // encoding: [0x09,0x42,0x38,0xd5]
+// CHECK: mrs      x9, {{SPSel|SPSEL}}                  // encoding: [0x09,0x42,0x38,0xd5]
 // CHECK: mrs      x9, {{nzcv|NZCV}}                   // encoding: [0x09,0x42,0x3b,0xd5]
 // CHECK: mrs      x9, {{daif|DAIF}}                   // encoding: [0x29,0x42,0x3b,0xd5]
-// CHECK: mrs      x9, {{currentel|CURRENTEL}}              // encoding: [0x49,0x42,0x38,0xd5]
-// CHECK: mrs      x9, {{spsr_irq|SPSR_IRQ}}               // encoding: [0x09,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, {{spsr_abt|SPSR_ABT}}               // encoding: [0x29,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, {{spsr_und|SPSR_UND}}               // encoding: [0x49,0x43,0x3c,0xd5]
-// CHECK: mrs      x9, {{spsr_fiq|SPSR_FIQ}}               // encoding: [0x69,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{CurrentEL|CURRENTEL}}              // encoding: [0x49,0x42,0x38,0xd5]
+// CHECK: mrs      x9, {{SPSR_irq|SPSR_IRQ}}               // encoding: [0x09,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{SPSR_abt|SPSR_ABT}}               // encoding: [0x29,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{SPSR_und|SPSR_UND}}               // encoding: [0x49,0x43,0x3c,0xd5]
+// CHECK: mrs      x9, {{SPSR_fiq|SPSR_FIQ}}               // encoding: [0x69,0x43,0x3c,0xd5]
 // CHECK: mrs      x9, {{fpcr|FPCR}}                   // encoding: [0x09,0x44,0x3b,0xd5]
 // CHECK: mrs      x9, {{fpsr|FPSR}}                   // encoding: [0x29,0x44,0x3b,0xd5]
 // CHECK: mrs      x9, {{dspsr_el0|DSPSR_EL0}}              // encoding: [0x09,0x45,0x3b,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
index 9027a60dd30..e31d3232951 100644
--- a/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
+++ b/llvm/test/MC/Disassembler/AArch64/arm64-system.txt
@@ -48,7 +48,7 @@
 # CHECK: sys #2, c0, c5, #7
 # CHECK: sys #7, c6, c10, #7, x7
 # CHECK: sysl  x20, #6, c3, c15, #7
-# CHECK: msr  SPSEL, #0
+# CHECK: msr  SPSel, #0
 # CHECK: msr S3_0_C11_C0_0, x0
 # CHECK: mrs x0, S3_0_C11_C0_0
 
diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
index 9d6723a96e4..4d438e032e7 100644
--- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
+++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
@@ -3131,9 +3131,9 @@
 0xdf 0x3f 0x3 0xd5
 0xdf 0x3c 0x3 0xd5
 
-# CHECK: msr      {{spsel|SPSEL}}, #0
-# CHECK: msr      {{daifset|DAIFSET}}, #15
-# CHECK: msr      {{daifclr|DAIFCLR}}, #12
+# CHECK: msr      {{SPSel|SPSEL}}, #0
+# CHECK: msr      {{DAIFSet|DAIFSET}}, #15
+# CHECK: msr      {{DAIFClr|DAIFCLR}}, #12
 0xbf 0x40 0x0 0xd5
 0xdf 0x4f 0x3 0xd5
 0xff 0x4c 0x3 0xd5
@@ -3289,14 +3289,14 @@
 # CHECK: msr      {{sp_el0|SP_EL0}}, x12
 # CHECK: msr      {{sp_el1|SP_EL1}}, x12
 # CHECK: msr      {{sp_el2|SP_EL2}}, x12
-# CHECK: msr      {{spsel|SPSEL}}, x12
+# CHECK: msr      {{SPSel|SPSEL}}, x12
 # CHECK: msr      {{nzcv|NZCV}}, x12
 # CHECK: msr      {{daif|DAIF}}, x12
-# CHECK: msr      {{currentel|CURRENTEL}}, x12
-# CHECK: msr      {{spsr_irq|SPSR_IRQ}}, x12
-# CHECK: msr      {{spsr_abt|SPSR_ABT}}, x12
-# CHECK: msr      {{spsr_und|SPSR_UND}}, x12
-# CHECK: msr      {{spsr_fiq|SPSR_FIQ}}, x12
+# CHECK: msr      {{CurrentEL|CURRENTEL}}, x12
+# CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12
+# CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12
+# CHECK: msr      {{SPSR_und|SPSR_UND}}, x12
+# CHECK: msr      {{SPSR_fiq|SPSR_FIQ}}, x12
 # CHECK: msr      {{fpcr|FPCR}}, x12
 # CHECK: msr      {{fpsr|FPSR}}, x12
 # CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12
@@ -3581,14 +3581,14 @@
 # CHECK: mrs      x9, {{sp_el0|SP_EL0}}
 # CHECK: mrs      x9, {{sp_el1|SP_EL1}}
 # CHECK: mrs      x9, {{sp_el2|SP_EL2}}
-# CHECK: mrs      x9, {{spsel|SPSEL}}
+# CHECK: mrs      x9, {{SPSel|SPSEL}}
 # CHECK: mrs      x9, {{nzcv|NZCV}}
 # CHECK: mrs      x9, {{daif|DAIF}}
-# CHECK: mrs      x9, {{currentel|CURRENTEL}}
-# CHECK: mrs      x9, {{spsr_irq|SPSR_IRQ}}
-# CHECK: mrs      x9, {{spsr_abt|SPSR_ABT}}
-# CHECK: mrs      x9, {{spsr_und|SPSR_UND}}
-# CHECK: mrs      x9, {{spsr_fiq|SPSR_FIQ}}
+# CHECK: mrs      x9, {{CurrentEL|CURRENTEL}}
+# CHECK: mrs      x9, {{SPSR_irq|SPSR_IRQ}}
+# CHECK: mrs      x9, {{SPSR_abt|SPSR_ABT}}
+# CHECK: mrs      x9, {{SPSR_und|SPSR_UND}}
+# CHECK: mrs      x9, {{SPSR_fiq|SPSR_FIQ}}
 # CHECK: mrs      x9, {{fpcr|FPCR}}
 # CHECK: mrs      x9, {{fpsr|FPSR}}
 # CHECK: mrs      x9, {{dspsr_el0|DSPSR_EL0}}