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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-16 23:21:55 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-16 23:21:55 +0000 |
| commit | 0ea1fce6b4c46b3874e96df4fe2bdf579cc212dd (patch) | |
| tree | 710c0cd062d535fc5129b7174d8bec7feba95879 /llvm/test/CodeGen/Thumb2 | |
| parent | c19bf0282de5a336de29aaecc29e8dad9c8906b2 (diff) | |
| download | bcm5719-llvm-0ea1fce6b4c46b3874e96df4fe2bdf579cc212dd.tar.gz bcm5719-llvm-0ea1fce6b4c46b3874e96df4fe2bdf579cc212dd.zip | |
Add ADD and SUB to the predicable ARM instructions.
It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.
Then the pseudo-instructions can go away.
llvm-svn: 162061
Diffstat (limited to 'llvm/test/CodeGen/Thumb2')
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll index 74729fd4150..ead198f2162 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -4,9 +4,9 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 ; CHECK: mvn r0, #-2147483648 ; CHECK: cmp r2, #10 -; CHECK: add r0, r1 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: addle.w r1, r1, r0 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 %tmp3 = add i32 %tmp2, %b @@ -15,10 +15,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t2 -; CHECK: add.w r0, r1, #-2147483648 ; CHECK: cmp r2, #10 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: addle.w r1, r1, #-2147483648 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483648 @@ -28,10 +28,10 @@ define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK: t3 -; CHECK: sub.w r0, r1, #10 ; CHECK: cmp r2, #10 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: suble.w r1, r1, #10 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 %tmp3 = sub i32 %b, %tmp2 |
