From 0ea1fce6b4c46b3874e96df4fe2bdf579cc212dd Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 16 Aug 2012 23:21:55 +0000 Subject: Add ADD and SUB to the predicable ARM instructions. It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061 --- llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'llvm/test/CodeGen/Thumb2') diff --git a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll index 74729fd4150..ead198f2162 100644 --- a/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/llvm/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -4,9 +4,9 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 ; CHECK: mvn r0, #-2147483648 ; CHECK: cmp r2, #10 -; CHECK: add r0, r1 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: addle.w r1, r1, r0 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483647 %tmp3 = add i32 %tmp2, %b @@ -15,10 +15,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t2 -; CHECK: add.w r0, r1, #-2147483648 ; CHECK: cmp r2, #10 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: addle.w r1, r1, #-2147483648 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 2147483648 @@ -28,10 +28,10 @@ define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind { define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK: t3 -; CHECK: sub.w r0, r1, #10 ; CHECK: cmp r2, #10 -; CHECK: it gt -; CHECK: movgt r0, r1 +; CHECK: it le +; CHECK: suble.w r1, r1, #10 +; CHECK: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 %tmp2 = select i1 %tmp1, i32 0, i32 10 %tmp3 = sub i32 %b, %tmp2 -- cgit v1.2.3