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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-18 19:21:56 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-18 19:21:56 +0000 |
| commit | efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf (patch) | |
| tree | 030850159ff5702742093390f74bac42c880388d /llvm/test | |
| parent | 0fa52c7db13bd0dec0b64776f57d7229f2e96486 (diff) | |
| download | bcm5719-llvm-efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf.tar.gz bcm5719-llvm-efc7c88ea8d0f5b0fa320c61ccb41ec2303aedbf.zip | |
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
This has the same issue as the early pass disabled in r321010.
llvm-svn: 321013
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-call.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/setcc-logic.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll index 231f29e6e4d..a080baedd8e 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-call.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-call.ll @@ -2,7 +2,7 @@ ; registers and with -fast-isel-abort=1 turned on the test case will then fail. ; When fastisel better supports VSX fix up this test case. ; -; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -mattr=-vsx -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-late-peephole=true | FileCheck %s --check-prefix=ELF64 define i32 @t1(i8 signext %a) nounwind { %1 = sext i8 %a to i32 diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll index d27538fb8d5..3b9b5228fa4 100644 --- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll +++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s +; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_clear: diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll index 89a248dc053..82c6c318abd 100644 --- a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll +++ b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-late-peephole=true < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ ; RUN: --check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ |
