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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 19:57:45 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-02-27 19:57:45 +0000 |
| commit | 982224cfb8de39337e977219b3571c5a87aca4ce (patch) | |
| tree | bab1498538efc732c8ef02877d6e289e7729e7e4 /llvm/test/CodeGen/AMDGPU | |
| parent | b7692bc3e9ad2691fc07261904b88fb15f30696b (diff) | |
| download | bcm5719-llvm-982224cfb8de39337e977219b3571c5a87aca4ce.tar.gz bcm5719-llvm-982224cfb8de39337e977219b3571c5a87aca4ce.zip | |
DAGCombiner: Don't unnecessarily swap operands in ReassociateOps
In the case where op = add, y = base_ptr, and x = offset, this
transform:
(op y, (op x, c1)) -> (op (op x, y), c1)
breaks the canonical form of add by putting the base pointer in the
second operand and the offset in the first.
This fix is important for the R600 target, because for some address
spaces the base pointer and the offset are stored in separate register
classes. The old pattern caused the ISel code for matching addressing
modes to put the base pointer and offset in the wrong register classes,
which required no-trivial code transformations to fix.
llvm-svn: 262148
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll | 33 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shl_add_constant.ll | 2 |
2 files changed, 34 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll new file mode 100644 index 00000000000..fc2834effb1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; Test for a bug where DAGCombiner::ReassociateOps() was creating adds +; with offset in the first operand and base pointers in the second. + +; CHECK-LABEL: {{^}}store_same_base_ptr: +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR:v\[[0-9]+:[0-9]+\]]], [[SADDR:s\[[0-9]+:[0-9]+\]]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] + +define void @store_same_base_ptr(i32 addrspace(1)* %out) { +entry: + %id = call i32 @llvm.amdgcn.workitem.id.x() #0 + %offset = sext i32 %id to i64 + %offset0 = add i64 %offset, 1027 + %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0 + store i32 3, i32 addrspace(1)* %ptr0 + %offset1 = add i64 %offset, 1026 + %ptr1 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset1 + store i32 2, i32 addrspace(1)* %ptr1 + %offset2 = add i64 %offset, 1025 + %ptr2 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset2 + store i32 1, i32 addrspace(1)* %ptr2 + %offset3 = add i64 %offset, 1024 + %ptr3 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset3 + store i32 0, i32 addrspace(1)* %ptr3 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll index ec17dbaaced..b1a3f8fbdc6 100644 --- a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll +++ b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll @@ -73,7 +73,7 @@ define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) # ; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3 -; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] +; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]] ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] ; SI: buffer_store_dword [[VRESULT]] |
