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| author | Quentin Colombet <qcolombet@apple.com> | 2016-07-13 20:36:03 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-07-13 20:36:03 +0000 |
| commit | 545e558b8209d1467ce0249ed9b5c45e6c81e8c5 (patch) | |
| tree | 1cef9dfc88aa4a886bf38c1f3279d23523274b5b /llvm/test/CodeGen/AMDGPU | |
| parent | 70ec1c7e62461ad559cc302adbd2f4e83e2fc264 (diff) | |
| download | bcm5719-llvm-545e558b8209d1467ce0249ed9b5c45e6c81e8c5.tar.gz bcm5719-llvm-545e558b8209d1467ce0249ed9b5c45e6c81e8c5.zip | |
[MIR] Print on the given output instead of stderr.
Currently the MIR framework prints all its outputs (errors and actual
representation) on stderr.
This patch fixes that by printing the regular output in the output
specified with -o.
Differential Revision: http://reviews.llvm.org/D22251
llvm-svn: 275314
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
4 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir index 8c761298cd2..f7f953c144d 100644 --- a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir +++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o /dev/null %s 2>&1 | FileCheck %s +# RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s --- | define void @test0() { ret void } define void @test1() { ret void } diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-undef.mir b/llvm/test/CodeGen/AMDGPU/indirect-addressing-undef.mir index 345cd681dc5..7cd35d41f30 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-lower-control-flow -o /dev/null %s 2>&1 | FileCheck %s +# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-lower-control-flow -o - %s | FileCheck %s # Getting an undef that is specifically a VGPR is tricky from IR # CHECK-LABEL: name: extract_undef_offset_vgpr{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir index e3858cc59a4..2dd21ca51e4 100644 --- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir +++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o /dev/null %s 2>&1 | FileCheck %s +# RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o - %s | FileCheck %s --- | define void @test0() { ret void } ... diff --git a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll index 45051d97608..98d1bb7cf9a 100644 --- a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll +++ b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -1,4 +1,4 @@ -; RUN: llc -o /dev/null %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos 2>&1 | FileCheck %s +; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s ; This test verifies that the instruction selection will add the implicit ; register operands in the correct order when modifying the opcode of an ; instruction to V_ADD_I32_e32. |
