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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-02 01:02:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-02 01:02:21 +0000 |
| commit | bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9 (patch) | |
| tree | c62d9f1ad3e9d80bea76cf9e408630ce548a8611 /llvm/test/CodeGen/AMDGPU/GlobalISel | |
| parent | 05aa8a733eebcb25c2ca8c0097544131f94cfb24 (diff) | |
| download | bcm5719-llvm-bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9.tar.gz bcm5719-llvm-bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9.zip | |
AMDGPU/GlobalISel: Private loads always use VGPRs
llvm-svn: 373414
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir index d129383817b..49ac13f6666 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir @@ -68,6 +68,7 @@ define amdgpu_kernel void @load_constant_i32_uniform_align4() {ret void} define amdgpu_kernel void @load_constant_i32_uniform_align2() {ret void} define amdgpu_kernel void @load_constant_i32_uniform_align1() {ret void} + define amdgpu_kernel void @load_private_uniform_sgpr_i32() {ret void} declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } @@ -635,3 +636,19 @@ body: | %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 1) ... + +--- +name: load_private_uniform_sgpr_i32 +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + + ; CHECK-LABEL: name: load_private_uniform_sgpr_i32 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY [[COPY]](p5) + ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p5) :: (load 4, addrspace 5) + %0:_(p5) = COPY $sgpr0 + %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5, align 4) +... |
