diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-02 01:02:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-02 01:02:21 +0000 |
| commit | bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9 (patch) | |
| tree | c62d9f1ad3e9d80bea76cf9e408630ce548a8611 /llvm | |
| parent | 05aa8a733eebcb25c2ca8c0097544131f94cfb24 (diff) | |
| download | bcm5719-llvm-bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9.tar.gz bcm5719-llvm-bfce0c2664dec15f9bd957ddc5ef25e13cd52fd9.zip | |
AMDGPU/GlobalISel: Private loads always use VGPRs
llvm-svn: 373414
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir | 17 |
2 files changed, 23 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 49a4c7b26b7..67a7f0a30c9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -447,8 +447,9 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings( unsigned PtrSize = PtrTy.getSizeInBits(); unsigned AS = PtrTy.getAddressSpace(); LLT LoadTy = MRI.getType(MI.getOperand(0).getReg()); - if (isInstrUniformNonExtLoadAlign4(MI) && - (AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS)) { + if ((AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS && + AS != AMDGPUAS::PRIVATE_ADDRESS) && + isInstrUniformNonExtLoadAlign4(MI)) { const InstructionMapping &SSMapping = getInstructionMapping( 1, 1, getOperandsMapping( {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), @@ -1853,8 +1854,9 @@ AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const { const ValueMapping *ValMapping; const ValueMapping *PtrMapping; - if (isInstrUniformNonExtLoadAlign4(MI) && - (AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS)) { + if ((AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS && + AS != AMDGPUAS::PRIVATE_ADDRESS) && + isInstrUniformNonExtLoadAlign4(MI)) { // We have a uniform instruction so we want to use an SMRD load ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir index d129383817b..49ac13f6666 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir @@ -68,6 +68,7 @@ define amdgpu_kernel void @load_constant_i32_uniform_align4() {ret void} define amdgpu_kernel void @load_constant_i32_uniform_align2() {ret void} define amdgpu_kernel void @load_constant_i32_uniform_align1() {ret void} + define amdgpu_kernel void @load_private_uniform_sgpr_i32() {ret void} declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } @@ -635,3 +636,19 @@ body: | %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 1) ... + +--- +name: load_private_uniform_sgpr_i32 +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + + ; CHECK-LABEL: name: load_private_uniform_sgpr_i32 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY [[COPY]](p5) + ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p5) :: (load 4, addrspace 5) + %0:_(p5) = COPY $sgpr0 + %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5, align 4) +... |
