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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:45:49 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 19:45:49 +0000 |
| commit | 3bfdb54d88d71b8cd8594d22d4b3712ee5661aa5 (patch) | |
| tree | 24d110844ec5be972d715a0ccd91fffd8256e818 /llvm/lib | |
| parent | 18b7133843bdfdfbad0f981c8cce944426e8411c (diff) | |
| download | bcm5719-llvm-3bfdb54d88d71b8cd8594d22d4b3712ee5661aa5.tar.gz bcm5719-llvm-3bfdb54d88d71b8cd8594d22d4b3712ee5661aa5.zip | |
AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
llvm-svn: 366118
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 0d02e738b4b..f916154c319 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -116,6 +116,10 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const { return RBI.constrainGenericRegister(DstReg, *RC, MRI); } + // TODO: Should probably leave the copy and let copyPhysReg expand it. + if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), MRI)) + return false; + BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) .addImm(0) .addReg(SrcReg); |
