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authorChris Lattner <sabre@nondot.org>2005-09-09 20:51:08 +0000
committerChris Lattner <sabre@nondot.org>2005-09-09 20:51:08 +0000
commitf540c1a2e8a4d84d576108b14b54767bc56c445a (patch)
tree5feb487ea1432e00b29888bb7aacc1a02062fce2 /llvm/lib/Target
parent141000375182366370840c77f249b16e6672e5c4 (diff)
downloadbcm5719-llvm-f540c1a2e8a4d84d576108b14b54767bc56c445a.tar.gz
bcm5719-llvm-f540c1a2e8a4d84d576108b14b54767bc56c445a.zip
code cleanup
llvm-svn: 23297
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
index a296d32866f..750d97978e2 100644
--- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
@@ -214,8 +214,9 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
// convert into indexed form of the instruction
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
- unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
- assert(NewOpcode && "No indexed form of load or store available!");
+ assert(ImmToIdxMap.count(MI.getOpcode()) &&
+ "No indexed form of load or store available!");
+ unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
MI.setOpcode(NewOpcode);
MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
MI.SetMachineOperandReg(2, PPC::R0);
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