From f540c1a2e8a4d84d576108b14b54767bc56c445a Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 9 Sep 2005 20:51:08 +0000 Subject: code cleanup llvm-svn: 23297 --- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp index a296d32866f..750d97978e2 100644 --- a/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp @@ -214,8 +214,9 @@ PPC32RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { // convert into indexed form of the instruction // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 - unsigned NewOpcode = const_cast& >(ImmToIdxMap)[MI.getOpcode()]; - assert(NewOpcode && "No indexed form of load or store available!"); + assert(ImmToIdxMap.count(MI.getOpcode()) && + "No indexed form of load or store available!"); + unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; MI.setOpcode(NewOpcode); MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); MI.SetMachineOperandReg(2, PPC::R0); -- cgit v1.2.3