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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 21:04:16 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 21:04:16 +0000 |
| commit | e30aa6a13623ca209aab966b71e56e7bdfc95722 (patch) | |
| tree | 6a79e2880516f84d2f6dbdd4c777f4b1827f3974 /llvm/lib/Target | |
| parent | d1477e989cef27ce486fc765ba3b3e5f0644cc6b (diff) | |
| download | bcm5719-llvm-e30aa6a13623ca209aab966b71e56e7bdfc95722.tar.gz bcm5719-llvm-e30aa6a13623ca209aab966b71e56e7bdfc95722.zip | |
[AMDGPU] Prepare for introduction of v3 and v5 MVTs
AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:
* Fixed assumptions of power-of-2 vector type in kernel arg handling,
and added v5 kernel arg tests and v3/v5 shader arg tests.
* Added v5 tests for cost analysis.
* Added vec3/vec5 arg test cases.
Some of this patch is from Matt Arsenault, also of AMD.
Differential Revision: https://reviews.llvm.org/D58928
Change-Id: I7279d6b4841464d2080eb255ef3c589e268eabcd
llvm-svn: 356342
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 141b76cc303..07ef8792477 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -1008,9 +1008,10 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute( if (MemVT.isVector() && MemVT.getVectorNumElements() == 1) MemVT = MemVT.getScalarType(); - if (MemVT.isExtended()) { - // This should really only happen if we have vec3 arguments - assert(MemVT.isVector() && MemVT.getVectorNumElements() == 3); + // Round up vec3/vec5 argument. + if (MemVT.isVector() && !MemVT.isPow2VectorType()) { + assert(MemVT.getVectorNumElements() == 3 || + MemVT.getVectorNumElements() == 5); MemVT = MemVT.getPow2VectorType(State.getContext()); } |
