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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 20:48:54 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-17 20:48:54 +0000 |
| commit | d1477e989cef27ce486fc765ba3b3e5f0644cc6b (patch) | |
| tree | 2b006d5dc10be0bff65745dd2e1754d39dadcd85 /llvm/lib/Target | |
| parent | 10ba65cc48f9420fe046b6a607642734394e7e6e (diff) | |
| download | bcm5719-llvm-d1477e989cef27ce486fc765ba3b3e5f0644cc6b.tar.gz bcm5719-llvm-d1477e989cef27ce486fc765ba3b3e5f0644cc6b.zip | |
[ARM] Fixed an assumption of power-of-2 vector MVT
I am about to introduce some non-power-of-2 width vector MVTs. This
commit fixes a power-of-2 assumption that my forthcoming change would
otherwise break, as shown by test/CodeGen/ARM/vcvt_combine.ll and
vdiv_combine.ll.
Differential Revision: https://reviews.llvm.org/D58927
Change-Id: I56a282e365d3874ab0621e5bdef98a612f702317
llvm-svn: 356341
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index bc985f744d8..b8e60028fd2 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -12154,11 +12154,11 @@ static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG, MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); uint32_t IntBits = IntTy.getSizeInBits(); unsigned NumLanes = Op.getValueType().getVectorNumElements(); - if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { + if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { // These instructions only exist converting from f32 to i32. We can handle // smaller integers by generating an extra truncate, but larger ones would - // be lossy. We also can't handle more then 4 lanes, since these intructions - // only support v2i32/v4i32 types. + // be lossy. We also can't handle anything other than 2 or 4 lanes, since + // these intructions only support v2i32/v4i32 types. return SDValue(); } @@ -12212,11 +12212,11 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); uint32_t IntBits = IntTy.getSizeInBits(); unsigned NumLanes = Op.getValueType().getVectorNumElements(); - if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { + if (FloatBits != 32 || IntBits > 32 || (NumLanes != 4 && NumLanes != 2)) { // These instructions only exist converting from i32 to f32. We can handle // smaller integers by generating an extra extend, but larger ones would - // be lossy. We also can't handle more then 4 lanes, since these intructions - // only support v2i32/v4i32 types. + // be lossy. We also can't handle anything other than 2 or 4 lanes, since + // these intructions only support v2i32/v4i32 types. return SDValue(); } |

