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authorKevin Enderby <enderby@apple.com>2014-04-08 18:00:52 +0000
committerKevin Enderby <enderby@apple.com>2014-04-08 18:00:52 +0000
commitd88fec3d3acc049d4fc5b83d5093b85a5f11ca81 (patch)
treeee722e81e825f2f1011a91d9c6f26c9b84908bb0 /llvm/lib/Target
parent6df5254d6f8b29fcd79030a30392a772d470f530 (diff)
downloadbcm5719-llvm-d88fec3d3acc049d4fc5b83d5093b85a5f11ca81.tar.gz
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Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index c4d53bb91f4..0ccb5beb7b8 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5901,7 +5901,7 @@ static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
- case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
+ case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
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