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authorMatt Arsenault <Matthew.Arsenault@amd.com>2017-02-16 02:01:17 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2017-02-16 02:01:17 +0000
commitd3e5cb77e4cbba5966479c62d970eb28414995a2 (patch)
treefbac4d061ad0590fddadd4e3cada9906879f4996
parentd2c8a337aa58d449bb5513245ab017f93e51b404 (diff)
downloadbcm5719-llvm-d3e5cb77e4cbba5966479c62d970eb28414995a2.tar.gz
bcm5719-llvm-d3e5cb77e4cbba5966479c62d970eb28414995a2.zip
AMDGPU: Remove llvm.SI.sendmsg
llvm-svn: 295270
-rw-r--r--llvm/lib/Target/AMDGPU/SIISelLowering.cpp7
-rw-r--r--llvm/lib/Target/AMDGPU/SIIntrinsics.td2
-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll62
3 files changed, 3 insertions, 68 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index e14cf35a49a..a8af1bb98a8 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2911,10 +2911,9 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
}
case Intrinsic::amdgcn_s_sendmsg:
- case Intrinsic::amdgcn_s_sendmsghalt:
- case AMDGPUIntrinsic::SI_sendmsg: {
- unsigned NodeOp = (IntrinsicID == Intrinsic::amdgcn_s_sendmsghalt) ?
- AMDGPUISD::SENDMSGHALT : AMDGPUISD::SENDMSG;
+ case Intrinsic::amdgcn_s_sendmsghalt: {
+ unsigned NodeOp = (IntrinsicID == Intrinsic::amdgcn_s_sendmsg) ?
+ AMDGPUISD::SENDMSG : AMDGPUISD::SENDMSGHALT;
Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
SDValue Glue = Chain.getValue(1);
return DAG.getNode(NodeOp, DL, MVT::Other, Chain,
diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td
index f98feeca430..5ea867c8fd0 100644
--- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td
+++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td
@@ -64,8 +64,6 @@ let TargetPrefix = "SI", isTarget = 1 in {
llvm_i32_ty], // tfe(imm)
[IntrReadMem, IntrArgMemOnly]>;
- def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
-
// Fully-flexible SAMPLE instruction.
class SampleRaw : Intrinsic <
[llvm_v4f32_ty], // vdata(VGPR)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
index 76df2ce5cfa..a1030b502bb 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll
@@ -121,69 +121,7 @@ body:
ret void
}
-; Legacy
-; GCN-LABEL: {{^}}test_legacy_interrupt:
-; GCN: s_mov_b32 m0, 0
-; GCN-NOT: s_mov_b32 m0
-; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
-define void @test_legacy_interrupt() {
-body:
- call void @llvm.SI.sendmsg(i32 1, i32 0)
- ret void
-}
-
-; GCN-LABEL: {{^}}test_legacy_gs_emit:
-; GCN: s_mov_b32 m0, 0
-; GCN-NOT: s_mov_b32 m0
-; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 0)
-define void @test_legacy_gs_emit() {
-body:
- call void @llvm.SI.sendmsg(i32 34, i32 0)
- ret void
-}
-
-; GCN-LABEL: {{^}}test_legacy_gs_cut:
-; GCN: s_mov_b32 m0, 0
-; GCN-NOT: s_mov_b32 m0
-; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1)
-define void @test_legacy_gs_cut() {
-body:
- call void @llvm.SI.sendmsg(i32 274, i32 0)
- ret void
-}
-
-; GCN-LABEL: {{^}}test_legacy_gs_emit_cut:
-; GCN: s_mov_b32 m0, 0
-; GCN-NOT: s_mov_b32 m0
-; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2)
-define void @test_legacy_gs_emit_cut() {
-body:
- call void @llvm.SI.sendmsg(i32 562, i32 0)
- ret void
-}
-
-; GCN-LABEL: {{^}}test_legacy_gs_done:
-; GCN: s_mov_b32 m0, 0
-; GCN-NOT: s_mov_b32 m0
-; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP)
-define void @test_legacy_gs_done() {
-body:
- call void @llvm.SI.sendmsg(i32 3, i32 0)
- ret void
-}
-
-; GCN-LABEL: {{^}}sendmsg_legacy:
-; GCN: s_mov_b32 m0, s0
-; VI-NEXT: s_nop 0
-; GCN-NEXT: sendmsg(MSG_GS_DONE, GS_OP_NOP)
-; GCN-NEXT: s_endpgm
-define amdgpu_gs void @sendmsg_legacy(i32 inreg %a) #0 {
- call void @llvm.SI.sendmsg(i32 3, i32 %a)
- ret void
-}
-
declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0
-declare void @llvm.SI.sendmsg(i32, i32) #0
attributes #0 = { nounwind }
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