diff options
| author | Thomas Lively <tlively@google.com> | 2018-09-26 00:34:36 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2018-09-26 00:34:36 +0000 |
| commit | c949857a7f4e08ff29db8e542e98884c044bf1ce (patch) | |
| tree | 4e628e1f6aaa79c4a0d19c51e153b090ddb6292b /llvm/lib/Target | |
| parent | 69ece336b8c06b71102e25f0d5770032d31b54cd (diff) | |
| download | bcm5719-llvm-c949857a7f4e08ff29db8e542e98884c044bf1ce.tar.gz bcm5719-llvm-c949857a7f4e08ff29db8e542e98884c044bf1ce.zip | |
[WebAssembly] SIMD conversions
Summary:
Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to
int conversions produce poison values if their arguments are out of
the convertible range, so a future CL will have to add an LLVM
intrinsic to make the saturating behavior of this conversion usable.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52372
llvm-svn: 343052
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td index a44a83995f6..490b9b2a043 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -218,6 +218,13 @@ multiclass SIMDSqrt<ValueType vec_t, string vec, bits<32> simdop> { [(set (vec_t V128:$dst), (vec_t (fsqrt V128:$vec)))], vec#".sqrt\t$dst, $vec", vec#".sqrt", simdop>; } +multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op, + string name, bits<32> simdop> { + defm op#_#vec_t#_#arg_t : + SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), + [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))], + name#"\t$dst, $vec", name, simdop>; +} let Defs = [ARGUMENTS] in { defm "" : ConstVec<v16i8, @@ -380,6 +387,15 @@ defm "" : SIMDAbs<v2f64, "f64x2", 128>; defm "" : SIMDSqrt<v4f32, "f32x4", 141>; defm "" : SIMDSqrt<v2f64, "f64x2", 142>; +defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_s?i32x4", 143>; +defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_u?i32x4", 144>; +defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_s?i64x2", 145>; +defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_u?i64x2", 146>; +defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_saturating_s?f32x4", 143>; +defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_saturating_u?f32x4", 144>; +defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_saturating_s?f64x2", 145>; +defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_saturating_u?f64x2", 146>; + } // Defs = [ARGUMENTS] // Def load and store patterns from WebAssemblyInstrMemory.td for vector types |
