[WebAssembly] SIMD conversions

Summary:
Lowers (s|u)itofp and fpto(s|u)i instructions for vectors. The fp to
int conversions produce poison values if their arguments are out of
the convertible range, so a future CL will have to add an LLVM
intrinsic to make the saturating behavior of this conversion usable.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52372

llvm-svn: 343052

3 files changed, 140 insertions, 0 deletions

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index a44a83995f6..490b9b2a043 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -218,6 +218,13 @@ multiclass SIMDSqrt<ValueType vec_t, string vec, bits<32> simdop> {
            [(set (vec_t V128:$dst), (vec_t (fsqrt V128:$vec)))],
            vec#".sqrt\t$dst, $vec", vec#".sqrt", simdop>;
 }
+multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
+                       string name, bits<32> simdop> {
+  defm op#_#vec_t#_#arg_t :
+    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
+           name#"\t$dst, $vec", name, simdop>;
+}
 
 let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
@@ -380,6 +387,15 @@ defm "" : SIMDAbs<v2f64, "f64x2", 128>;
 defm "" : SIMDSqrt<v4f32, "f32x4", 141>;
 defm "" : SIMDSqrt<v2f64, "f64x2", 142>;
 
+defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_s?i32x4", 143>;
+defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_u?i32x4", 144>;
+defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_s?i64x2", 145>;
+defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_u?i64x2", 146>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_saturating_s?f32x4", 143>;
+defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_saturating_u?f32x4", 144>;
+defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_saturating_s?f64x2", 145>;
+defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_saturating_u?f64x2", 146>;
+
 } // Defs = [ARGUMENTS]
 
 // Def load and store patterns from WebAssemblyInstrMemory.td for vector types
diff --git a/llvm/test/CodeGen/WebAssembly/simd-conversions.ll b/llvm/test/CodeGen/WebAssembly/simd-conversions.ll
new file mode 100644
index 00000000000..db2c7afa5c3
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-conversions.ll
@@ -0,0 +1,100 @@
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
+; Test that vector float-to-int and int-to-float instructions lower correctly
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: convert_s_v4f32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.convert_s?i32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x float> @convert_s_v4f32(<4 x i32> %x) {
+  %a = sitofp <4 x i32> %x to <4 x float>
+  ret <4 x float> %a
+}
+
+; CHECK-LABEL: convert_u_v4f32:
+; NO-SIMD128-NOT: i32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.convert_u?i32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x float> @convert_u_v4f32(<4 x i32> %x) {
+  %a = uitofp <4 x i32> %x to <4 x float>
+  ret <4 x float> %a
+}
+
+; CHECK-LABEL: convert_s_v2f64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: f64x2.convert_s?i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.convert_s?i64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x double> @convert_s_v2f64(<2 x i64> %x) {
+  %a = sitofp <2 x i64> %x to <2 x double>
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: convert_u_v2f64:
+; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: f64x2.convert_u?i64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.convert_u?i64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x double> @convert_u_v2f64(<2 x i64> %x) {
+  %a = uitofp <2 x i64> %x to <2 x double>
+  ret <2 x double> %a
+}
+
+; CHECK-LABEL: trunc_saturating_s_v4i32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.trunc_saturating_s?f32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x i32> @trunc_saturating_s_v4i32(<4 x float> %x) {
+  %a = fptosi <4 x float> %x to <4 x i32>
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: trunc_saturating_u_v4i32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i32x4.trunc_saturating_u?f32x4 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <4 x i32> @trunc_saturating_u_v4i32(<4 x float> %x) {
+  %a = fptoui <4 x float> %x to <4 x i32>
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: trunc_saturating_s_v2i64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: i64x2.trunc_saturating_s?f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i64x2.trunc_saturating_s?f64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x i64> @trunc_saturating_s_v2i64(<2 x double> %x) {
+  %a = fptosi <2 x double> %x to <2 x i64>
+  ret <2 x i64> %a
+}
+
+; CHECK-LABEL: trunc_saturating_u_v2i64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: i64x2.trunc_saturating_u?f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: i64x2.trunc_saturating_u?f64x2 $push[[R:[0-9]+]]=, $0
+; SIMD128-NEXT: return $pop[[R]]
+define <2 x i64> @trunc_saturating_u_v2i64(<2 x double> %x) {
+  %a = fptoui <2 x double> %x to <2 x i64>
+  ret <2 x i64> %a
+}
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index 6c4e45c216a..92198d9f99a 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -361,4 +361,28 @@
     # CHECK: f64x2.sqrt # encoding: [0xfd,0x8e]
     f64x2.sqrt
 
+    # CHECK: f32x4.convert_s?i32x4 # encoding: [0xfd,0x8f]
+    f32x4.convert_s?i32x4
+
+    # CHECK: f32x4.convert_u?i32x4 # encoding: [0xfd,0x90]
+    f32x4.convert_u?i32x4
+
+    # CHECK: f64x2.convert_s?i64x2 # encoding: [0xfd,0x91]
+    f64x2.convert_s?i64x2
+
+    # CHECK: f64x2.convert_u?i64x2 # encoding: [0xfd,0x92]
+    f64x2.convert_u?i64x2
+
+    # CHECK? i32x4.trunc_saturating_s?f32x4 # encoding: [0xfd,0x93]
+    i32x4.trunc_saturating_s?f32x4
+
+    # CHECK? i32x4.trunc_saturating_u?f32x4 # encoding: [0xfd,0x94]
+    i32x4.trunc_saturating_u?f32x4
+
+    # CHECK? i64x2.trunc_saturating_s?f64x2 # encoding: [0xfd,0x95]
+    i64x2.trunc_saturating_s?f64x2
+
+    # CHECK? i64x2.trunc_saturating_u?f64x2 # encoding: [0xfd,0x96]
+    i64x2.trunc_saturating_u?f64x2
+
     end_function