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| author | Craig Topper <craig.topper@intel.com> | 2019-04-19 05:48:13 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-04-19 05:48:13 +0000 |
| commit | bb769a29467b51c391a0149ea7301e71c0569a71 (patch) | |
| tree | 056dec9ae9fc4d5464fced1aa4ab4c4ae8b8b794 /llvm/lib/Target | |
| parent | 2099ccbe1ffbc0a71fef992ad8ad15164c450cc0 (diff) | |
| download | bcm5719-llvm-bb769a29467b51c391a0149ea7301e71c0569a71.tar.gz bcm5719-llvm-bb769a29467b51c391a0149ea7301e71c0569a71.zip | |
[X86] Turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the AND could match a movzx.
Could get further improvements by recognizing (i64 and (anyext (i32 shl))).
llvm-svn: 358737
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 67ba3c50a3a..c98cea8a74b 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -4009,6 +4009,9 @@ void X86DAGToDAGISel::Select(SDNode *Node) { ShiftedVal = (uint64_t)Val >> ShAmt; if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) return true; + // Also swap order when the AND can become MOVZX. + if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) + return true; } ShiftedVal = Val >> ShAmt; if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || |
