diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/narrow-shl-cst.ll | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 67ba3c50a3a..c98cea8a74b 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -4009,6 +4009,9 @@ void X86DAGToDAGISel::Select(SDNode *Node) { ShiftedVal = (uint64_t)Val >> ShAmt; if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) return true; + // Also swap order when the AND can become MOVZX. + if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) + return true; } ShiftedVal = Val >> ShAmt; if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || diff --git a/llvm/test/CodeGen/X86/narrow-shl-cst.ll b/llvm/test/CodeGen/X86/narrow-shl-cst.ll index 0100a8ce772..86fc7a17e5d 100644 --- a/llvm/test/CodeGen/X86/narrow-shl-cst.ll +++ b/llvm/test/CodeGen/X86/narrow-shl-cst.ll @@ -201,9 +201,8 @@ define i64 @test16(i64 %x, i64* %y) nounwind { define i32 @test17(i32 %x) nounwind { ; CHECK-LABEL: test17: ; CHECK: # %bb.0: -; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: shll $10, %eax -; CHECK-NEXT: andl $261120, %eax # imm = 0x3FC00 ; CHECK-NEXT: retq %and = shl i32 %x, 10 %shl = and i32 %and, 261120 @@ -225,9 +224,8 @@ define i64 @test18(i64 %x) nounwind { define i32 @test19(i32 %x) nounwind { ; CHECK-LABEL: test19: ; CHECK: # %bb.0: -; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: movzwl %di, %eax ; CHECK-NEXT: shll $10, %eax -; CHECK-NEXT: andl $67107840, %eax # imm = 0x3FFFC00 ; CHECK-NEXT: retq %and = shl i32 %x, 10 %shl = and i32 %and, 67107840 |
