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| author | Craig Topper <craig.topper@intel.com> | 2018-03-22 22:17:11 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-22 22:17:11 +0000 |
| commit | adb173314dd65ef9f84e1d22ec1ac4f2582f3031 (patch) | |
| tree | 7729e38c4e7faea9867ebde9ce5712249631f8cd | |
| parent | 376294c23a047c19097a0603c3890ebdda86bff8 (diff) | |
| download | bcm5719-llvm-adb173314dd65ef9f84e1d22ec1ac4f2582f3031.tar.gz bcm5719-llvm-adb173314dd65ef9f84e1d22ec1ac4f2582f3031.zip | |
[X86] Correct the VROUND regular expressions in Znver1 scheduler model to account for r328254
llvm-svn: 328260
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/avx-schedule.ll | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index d2f3dacf38c..2ed0008757b 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1610,14 +1610,14 @@ def : InstRW<[ZnWriteVRCPPSLd], (instregex "VRCPPSYm")>; def ZnWriteROUNDr : SchedWriteRes<[ZnFPU3]> { let Latency = 4; } -def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r")>; +def : InstRW<[ZnWriteROUNDr], (instregex "(V?)ROUND(S|P)(S|D)(Y?)r")>; // v,m,i. def ZnWriteROUNDm : SchedWriteRes<[ZnAGU, ZnFPU3]> { let Latency = 11; let NumMicroOps = 2; } -def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m")>; +def : InstRW<[ZnWriteROUNDm], (instregex "(V?)ROUND(S|P)(S|D)(Y?)m")>; // DPPS. // x,x,i / v,v,v,i. diff --git a/llvm/test/CodeGen/X86/avx-schedule.ll b/llvm/test/CodeGen/X86/avx-schedule.ll index 7df419d5185..6a4ab314f06 100644 --- a/llvm/test/CodeGen/X86/avx-schedule.ll +++ b/llvm/test/CodeGen/X86/avx-schedule.ll @@ -4132,8 +4132,8 @@ define <4 x double> @test_roundpd(<4 x double> %a0, <4 x double> *%a1) { ; ; ZNVER1-LABEL: test_roundpd: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [10:1.00] -; ZNVER1-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [3:1.00] +; ZNVER1-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [11:1.00] +; ZNVER1-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [4:1.00] ; ZNVER1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00] ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) @@ -4196,8 +4196,8 @@ define <8 x float> @test_roundps(<8 x float> %a0, <8 x float> *%a1) { ; ; ZNVER1-LABEL: test_roundps: ; ZNVER1: # %bb.0: -; ZNVER1-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [10:1.00] -; ZNVER1-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [3:1.00] +; ZNVER1-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [11:1.00] +; ZNVER1-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [4:1.00] ; ZNVER1-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00] ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) |
