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| author | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:13 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:13 +0000 |
| commit | a59a886832bd223127f5c7edf2cf729ba6857fe7 (patch) | |
| tree | 59f5249fef0e8510ea79151891caefdc6d27c423 /llvm/lib/Target | |
| parent | fae979bc682bdb21a9bdf2e4170ee54afabee5c7 (diff) | |
| download | bcm5719-llvm-a59a886832bd223127f5c7edf2cf729ba6857fe7.tar.gz bcm5719-llvm-a59a886832bd223127f5c7edf2cf729ba6857fe7.zip | |
[AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>
Just add an extra case to the existing selection logic.
llvm-svn: 372466
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 8503a0dbb06..223aa370e97 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1052,7 +1052,11 @@ bool AArch64InstructionSelector::selectVectorASHR( unsigned Opc = 0; unsigned NegOpc = 0; const TargetRegisterClass *RC = nullptr; - if (Ty == LLT::vector(4, 32)) { + if (Ty == LLT::vector(2, 64)) { + Opc = AArch64::SSHLv2i64; + NegOpc = AArch64::NEGv2i64; + RC = &AArch64::FPR128RegClass; + } else if (Ty == LLT::vector(4, 32)) { Opc = AArch64::SSHLv4i32; NegOpc = AArch64::NEGv4i32; RC = &AArch64::FPR128RegClass; |
