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| author | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:13 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-09-21 09:21:13 +0000 |
| commit | a59a886832bd223127f5c7edf2cf729ba6857fe7 (patch) | |
| tree | 59f5249fef0e8510ea79151891caefdc6d27c423 | |
| parent | fae979bc682bdb21a9bdf2e4170ee54afabee5c7 (diff) | |
| download | bcm5719-llvm-a59a886832bd223127f5c7edf2cf729ba6857fe7.tar.gz bcm5719-llvm-a59a886832bd223127f5c7edf2cf729ba6857fe7.zip | |
[AArch64][GlobalISel] Selection support for G_ASHR of <2 x s64>
Just add an extra case to the existing selection logic.
llvm-svn: 372466
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir | 30 |
2 files changed, 35 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 8503a0dbb06..223aa370e97 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1052,7 +1052,11 @@ bool AArch64InstructionSelector::selectVectorASHR( unsigned Opc = 0; unsigned NegOpc = 0; const TargetRegisterClass *RC = nullptr; - if (Ty == LLT::vector(4, 32)) { + if (Ty == LLT::vector(2, 64)) { + Opc = AArch64::SSHLv2i64; + NegOpc = AArch64::NEGv2i64; + RC = &AArch64::FPR128RegClass; + } else if (Ty == LLT::vector(4, 32)) { Opc = AArch64::SSHLv4i32; NegOpc = AArch64::NEGv4i32; RC = &AArch64::FPR128RegClass; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir index 95da841e71d..b13c4b5ec0d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir @@ -118,3 +118,33 @@ body: | RET_ReallyLR implicit $q0 ... +--- +name: ashr_v4i64 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +registers: + - { id: 0, class: fpr } + - { id: 1, class: fpr } + - { id: 2, class: fpr } +machineFunctionInfo: {} +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: ashr_v4i64 + ; CHECK: liveins: $q0, $q1 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]] + ; CHECK: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]] + ; CHECK: $q0 = COPY [[SSHLv2i64_]] + ; CHECK: RET_ReallyLR implicit $q0 + %0:fpr(<2 x s64>) = COPY $q0 + %1:fpr(<2 x s64>) = COPY $q1 + %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>) + $q0 = COPY %2(<2 x s64>) + RET_ReallyLR implicit $q0 + +... |
