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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:37:39 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:37:39 +0000 |
| commit | 89fc8bcdd6d20e845b6bd297dce0e2542cd1156c (patch) | |
| tree | a33ba838bfae73590dfb7ea070654a990010194c /llvm/lib/Target | |
| parent | 3b7668ae4bb8fabf95bd78dc6a06ca75f6ec3958 (diff) | |
| download | bcm5719-llvm-89fc8bcdd6d20e845b6bd297dce0e2542cd1156c.tar.gz bcm5719-llvm-89fc8bcdd6d20e845b6bd297dce0e2542cd1156c.zip | |
AMDGPU/GlobalISel: Fail on store to 32-bit address space
llvm-svn: 364766
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index b776b4137df..ece01b511cd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -549,6 +549,12 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); DebugLoc DL = I.getDebugLoc(); + unsigned PtrSize = RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI); + if (PtrSize != 64) { + LLVM_DEBUG(dbgs() << "Unhandled address space\n"); + return false; + } + unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); unsigned Opcode; |
