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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:37:39 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-01 13:37:39 +0000 |
| commit | 89fc8bcdd6d20e845b6bd297dce0e2542cd1156c (patch) | |
| tree | a33ba838bfae73590dfb7ea070654a990010194c | |
| parent | 3b7668ae4bb8fabf95bd78dc6a06ca75f6ec3958 (diff) | |
| download | bcm5719-llvm-89fc8bcdd6d20e845b6bd297dce0e2542cd1156c.tar.gz bcm5719-llvm-89fc8bcdd6d20e845b6bd297dce0e2542cd1156c.zip | |
AMDGPU/GlobalISel: Fail on store to 32-bit address space
llvm-svn: 364766
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 |
2 files changed, 9 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index b776b4137df..ece01b511cd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -549,6 +549,12 @@ bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const { MachineFunction *MF = BB->getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); DebugLoc DL = I.getDebugLoc(); + unsigned PtrSize = RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI); + if (PtrSize != 64) { + LLVM_DEBUG(dbgs() << "Unhandled address space\n"); + return false; + } + unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI); unsigned Opcode; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir index 3fde1f04a8c..6edd3fa10ff 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir @@ -119,9 +119,9 @@ regBankSelected: true body: | bb.0: ; GCN-LABEL: name: implicit_def_p3_vgpr - ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec - ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr + ; GCN: [[DEF:%[0-9]+]]:vgpr(p3) = G_IMPLICIT_DEF + ; GCN: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4 + ; GCN: G_STORE [[C]](s32), [[DEF]](p3) :: (store 4, addrspace 1) %0:vgpr(p3) = G_IMPLICIT_DEF %1:vgpr(s32) = G_CONSTANT i32 4 G_STORE %1, %0 :: (store 4, addrspace 1) |
