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author | Tom Stellard <tstellar@redhat.com> | 2018-06-13 22:30:47 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-06-13 22:30:47 +0000 |
commit | 46bbbc33c02fefcb48fdf25e7db43576fb0e245f (patch) | |
tree | f38055b1f161d601e0e2b520d9688a5ec90180fe /llvm/lib/Target | |
parent | dd2f78e34cdc5e5cbad8c293b5422c0efe9f5063 (diff) | |
download | bcm5719-llvm-46bbbc33c02fefcb48fdf25e7db43576fb0e245f.tar.gz bcm5719-llvm-46bbbc33c02fefcb48fdf25e7db43576fb0e245f.zip |
AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46171
llvm-svn: 334665
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 4 | ||||
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 10 | ||||
-rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 2 |
3 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index c9dfbafab0c..f27f52eb9be 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -22,6 +22,10 @@ def gi_vop3mods0 : GIComplexOperandMatcher<s32, "selectVOP3Mods0">, GIComplexPatternEquiv<VOP3Mods0>; +def gi_vop3mods : + GIComplexOperandMatcher<s32, "selectVOP3Mods">, + GIComplexPatternEquiv<VOP3Mods>; + class GISelSop2Pat < SDPatternOperator node, Instruction inst, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ab8424440dd..c3dee4e55dc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -508,6 +508,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, switch (I.getOpcode()) { default: break; + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FADD: case TargetOpcode::G_FPTOUI: case TargetOpcode::G_OR: return selectImpl(I, CoverageInfo); @@ -547,3 +549,11 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod }}; } + +InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const { + return {{ + [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods + }}; +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index cdad743ff22..b304ec2f783 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -75,6 +75,8 @@ private: InstructionSelector::ComplexRendererFns selectVOP3Mods0(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectVOP3Mods(MachineOperand &Root) const; const SIInstrInfo &TII; const SIRegisterInfo &TRI; |