diff options
5 files changed, 90 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index c9dfbafab0c..f27f52eb9be 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -22,6 +22,10 @@ def gi_vop3mods0 : GIComplexOperandMatcher<s32, "selectVOP3Mods0">, GIComplexPatternEquiv<VOP3Mods0>; +def gi_vop3mods : + GIComplexOperandMatcher<s32, "selectVOP3Mods">, + GIComplexPatternEquiv<VOP3Mods>; + class GISelSop2Pat < SDPatternOperator node, Instruction inst, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ab8424440dd..c3dee4e55dc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -508,6 +508,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, switch (I.getOpcode()) { default: break; + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FADD: case TargetOpcode::G_FPTOUI: case TargetOpcode::G_OR: return selectImpl(I, CoverageInfo); @@ -547,3 +549,11 @@ AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod }}; } + +InstructionSelector::ComplexRendererFns +AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const { + return {{ + [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods + }}; +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index cdad743ff22..b304ec2f783 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -75,6 +75,8 @@ private: InstructionSelector::ComplexRendererFns selectVOP3Mods0(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectVOP3Mods(MachineOperand &Root) const; const SIInstrInfo &TII; const SIRegisterInfo &TRI; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir new file mode 100644 index 00000000000..01a59f05a61 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir @@ -0,0 +1,37 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @fadd(i32 addrspace(1)* %global0) {ret void} +... +--- + +name: fadd +legalized: true +regBankSelected: true + +# GCN-LABEL: name: fadd +body: | + bb.0: + liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4 + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = COPY $vgpr0 + %2:vgpr(s32) = COPY $vgpr1 + %3:vgpr(s64) = COPY $vgpr3_vgpr4 + + ; fadd vs + ; GCN: V_ADD_F32_e64 + %4:vgpr(s32) = G_FADD %1, %0 + + ; fadd sv + ; GCN: V_ADD_F32_e64 + %5:vgpr(s32) = G_FADD %0, %1 + + ; fadd vv + ; GCN: V_ADD_F32_e64 + %6:vgpr(s32) = G_FADD %1, %2 + + G_STORE %4, %3 :: (store 4 into %ir.global0) + G_STORE %5, %3 :: (store 4 into %ir.global0) + G_STORE %6, %3 :: (store 4 into %ir.global0) +... +--- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir new file mode 100644 index 00000000000..b7e472abc93 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir @@ -0,0 +1,37 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @fmul(i32 addrspace(1)* %global0) {ret void} +... +--- + +name: fmul +legalized: true +regBankSelected: true + +# GCN-LABEL: name: fmul +body: | + bb.0: + liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4 + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = COPY $vgpr0 + %2:vgpr(s32) = COPY $vgpr1 + %3:vgpr(s64) = COPY $vgpr3_vgpr4 + + ; fmul vs + ; GCN: V_MUL_F32_e64 + %4:vgpr(s32) = G_FMUL %1, %0 + + ; fmul sv + ; GCN: V_MUL_F32_e64 + %5:vgpr(s32) = G_FMUL %0, %1 + + ; fmul vv + ; GCN: V_MUL_F32_e64 + %6:vgpr(s32) = G_FMUL %1, %2 + + G_STORE %4, %3 :: (store 4 into %ir.global0) + G_STORE %5, %3 :: (store 4 into %ir.global0) + G_STORE %6, %3 :: (store 4 into %ir.global0) +... +--- |
