summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-03-07 23:12:04 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2017-03-07 23:12:04 +0000
commit434d50a7960f85eda5b744a5c6b6aed650ccfc3c (patch)
tree86ebcb15f716e39a8e5652345d6cac4362e4a75f /llvm/lib/Target
parent8e4d2e0512a96f0d8e000354b2222aa2ae2d0e70 (diff)
downloadbcm5719-llvm-434d50a7960f85eda5b744a5c6b6aed650ccfc3c.tar.gz
bcm5719-llvm-434d50a7960f85eda5b744a5c6b6aed650ccfc3c.zip
[Hexagon] Check for presence before looking registers up in bit tracker
llvm-svn: 297240
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 28784f0aa31..5fef6083552 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2216,6 +2216,8 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
for (unsigned S = AVs.find_first(); S; S = AVs.find_next(S)) {
// The number of leading zeros here should be the number of trailing
// non-zeros in RC.
+ if (!BT.has(S))
+ continue;
const BitTracker::RegisterCell &SC = BT.lookup(S);
if (SC.width() != W || ctlz(SC) != W-Z)
continue;
@@ -2421,6 +2423,8 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
bool Changed = false;
for (unsigned R = AVs.find_first(); R != 0; R = AVs.find_next(R)) {
+ if (!BT.has(R))
+ continue;
const BitTracker::RegisterCell &SC = BT.lookup(R);
unsigned SW = SC.width();
OpenPOWER on IntegriCloud