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authorPetar Jovanovic <petar.jovanovic@mips.com>2018-01-22 16:43:30 +0000
committerPetar Jovanovic <petar.jovanovic@mips.com>2018-01-22 16:43:30 +0000
commit29aced1baed029fa3f68c103ca203546033d0b6f (patch)
tree2e637be04e9bad45390b05bd90663202268f3c17 /llvm/lib/Target
parentf94c10d91a95b0fe5d529b72280b7f52773ed740 (diff)
downloadbcm5719-llvm-29aced1baed029fa3f68c103ca203546033d0b6f.tar.gz
bcm5719-llvm-29aced1baed029fa3f68c103ca203546033d0b6f.zip
[mips] add warnings for using dsp and msa flags with inappropriate revisions
Dsp and dspr2 require MIPS revision 2, while msa requires revision 5. Adding warnings for cases when these flags are used with earlier revision. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D40490 llvm-svn: 323131
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp38
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.h6
2 files changed, 44 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index f6af7e22e35..cbc2ef79e4f 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -57,6 +57,10 @@ static cl::opt<bool>
GPOpt("mgpopt", cl::Hidden,
cl::desc("Enable gp-relative addressing of mips small data items"));
+bool MipsSubtarget::DspWarningPrinted = false;
+
+bool MipsSubtarget::MSAWarningPrinted = false;
+
void MipsSubtarget::anchor() {}
MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
@@ -129,6 +133,40 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
<< "\n";
UseSmallSection = false;
}
+
+ if (hasDSPR2() && !DspWarningPrinted) {
+ if (hasMips64() && !hasMips64r2()) {
+ errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
+ << "greater\n";
+ DspWarningPrinted = true;
+ } else if (hasMips32() && !hasMips32r2()) {
+ errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
+ << "greater\n";
+ DspWarningPrinted = true;
+ }
+ } else if (hasDSP() && !DspWarningPrinted) {
+ if (hasMips64() && !hasMips64r2()) {
+ errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
+ << "greater\n";
+ DspWarningPrinted = true;
+ } else if (hasMips32() && !hasMips32r2()) {
+ errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
+ << "greater\n";
+ DspWarningPrinted = true;
+ }
+ }
+
+ if (hasMSA() && !MSAWarningPrinted) {
+ if (hasMips64() && !hasMips64r5()) {
+ errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or "
+ << "greater\n";
+ MSAWarningPrinted = true;
+ } else if (hasMips32() && !hasMips32r5()) {
+ errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or "
+ << "greater\n";
+ MSAWarningPrinted = true;
+ }
+ }
}
bool MipsSubtarget::isPositionIndependent() const {
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 8b10b0596e0..bdf71fce85a 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -44,6 +44,12 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
enum class CPU { P5600 };
+ // Used to avoid printing dsp warnings multiple times.
+ static bool DspWarningPrinted;
+
+ // Used to avoid printing msa warnings multiple times.
+ static bool MSAWarningPrinted;
+
// Mips architecture version
MipsArchEnum MipsArchVersion;
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