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author | Alex Bradbury <asb@lowrisc.org> | 2018-04-26 13:37:00 +0000 |
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committer | Alex Bradbury <asb@lowrisc.org> | 2018-04-26 13:37:00 +0000 |
commit | 130b8b3f2b49a0c04f5acb8e56c0f75245e222e8 (patch) | |
tree | f4fc580683a666c2112e864e83d936a0cbae9d71 /llvm/lib/Target | |
parent | a331f9185312e4d317f02e13a6203479023c37e1 (diff) | |
download | bcm5719-llvm-130b8b3f2b49a0c04f5acb8e56c0f75245e222e8.tar.gz bcm5719-llvm-130b8b3f2b49a0c04f5acb8e56c0f75245e222e8.zip |
[RISCV] Implement isTruncateFree
Adapted from ARM's implementation introduced in r313533 and r314280.
llvm-svn: 330940
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 20 | ||||
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 |
2 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 16b4bddcd5c..d1ad453fbf8 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -191,6 +191,26 @@ bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const { return isInt<12>(Imm); } +// On RV32, 64-bit integers are split into their high and low parts and held +// in two different registers, so the trunc is free since the low register can +// just be used. +bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { + if (Subtarget.is64Bit() || !SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) + return false; + unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); + unsigned DestBits = DstTy->getPrimitiveSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} + +bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { + if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || + !SrcVT.isInteger() || !DstVT.isInteger()) + return false; + unsigned SrcBits = SrcVT.getSizeInBits(); + unsigned DestBits = DstVT.getSizeInBits(); + return (SrcBits == 64 && DestBits == 32); +} + // Changes the condition code and swaps operands if necessary, so the SetCC // operation matches one of the comparisons supported directly in the RISC-V // ISA. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index dccd0315bbf..2a2016ef5f5 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -44,6 +44,8 @@ public: Instruction *I = nullptr) const override; bool isLegalICmpImmediate(int64_t Imm) const override; bool isLegalAddImmediate(int64_t Imm) const override; + bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; + bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; // Provide custom lowering hooks for some operations. SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; |