summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorLama Saba <lama.saba@intel.com>2018-04-26 13:16:11 +0000
committerLama Saba <lama.saba@intel.com>2018-04-26 13:16:11 +0000
commita331f9185312e4d317f02e13a6203479023c37e1 (patch)
treef0793e48e5e04a6452cc27445698bb9daad31cbd /llvm/lib/Target
parentdcbff63c24e6262244f1c8cbaa6a8ffae61ffd6d (diff)
downloadbcm5719-llvm-a331f9185312e4d317f02e13a6203479023c37e1.tar.gz
bcm5719-llvm-a331f9185312e4d317f02e13a6203479023c37e1.zip
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
Differential Revision: https://reviews.llvm.org/D45823 Change-Id: Icf6f34f6babc3cb2ff5292fde003472473037a71 llvm-svn: 330939
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp48
1 files changed, 29 insertions, 19 deletions
diff --git a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
index 355fae32876..bf6cc6728cb 100644
--- a/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
+++ b/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
@@ -395,30 +395,40 @@ void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
unsigned Reg1 = MRI->createVirtualRegister(
TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
- BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode), Reg1)
- .add(LoadBase)
- .addImm(1)
- .addReg(X86::NoRegister)
- .addImm(LoadDisp)
- .addReg(X86::NoRegister)
- .addMemOperand(
- MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size));
- DEBUG(LoadInst->getPrevNode()->dump());
+ MachineInstr *NewLoad =
+ BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode),
+ Reg1)
+ .add(LoadBase)
+ .addImm(1)
+ .addReg(X86::NoRegister)
+ .addImm(LoadDisp)
+ .addReg(X86::NoRegister)
+ .addMemOperand(
+ MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size));
+ if (LoadBase.isReg())
+ getBaseOperand(NewLoad).setIsKill(false);
+ DEBUG(NewLoad->dump());
// If the load and store are consecutive, use the loadInst location to
// reduce register pressure.
MachineInstr *StInst = StoreInst;
if (StoreInst->getPrevNode() == LoadInst)
StInst = LoadInst;
- BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
- .add(StoreBase)
- .addImm(1)
- .addReg(X86::NoRegister)
- .addImm(StoreDisp)
- .addReg(X86::NoRegister)
- .addReg(Reg1)
- .addMemOperand(
- MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size));
- DEBUG(StInst->getPrevNode()->dump());
+ MachineInstr *NewStore =
+ BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
+ .add(StoreBase)
+ .addImm(1)
+ .addReg(X86::NoRegister)
+ .addImm(StoreDisp)
+ .addReg(X86::NoRegister)
+ .addReg(Reg1)
+ .addMemOperand(
+ MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size));
+ if (StoreBase.isReg())
+ getBaseOperand(NewStore).setIsKill(false);
+ MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands);
+ assert(StoreSrcVReg.isReg() && "Expected virtual register");
+ NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill());
+ DEBUG(NewStore->dump());
}
void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst,
OpenPOWER on IntegriCloud