summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
diff options
context:
space:
mode:
authorHal Finkel <hfinkel@anl.gov>2013-03-27 06:52:27 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-27 06:52:27 +0000
commit0f77861d9f25c8d5212a2cee7729a6c6e448864d (patch)
tree5ca2d97841cfd647adf47e7e09e1b783df1ee7b9 /llvm/lib/Target
parent953c701b8b96aad1078cee68df377f47ebfb61d5 (diff)
downloadbcm5719-llvm-0f77861d9f25c8d5212a2cee7729a6c6e448864d.tar.gz
bcm5719-llvm-0f77861d9f25c8d5212a2cee7729a6c6e448864d.zip
Allocate r0 on PPC
The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. llvm-svn: 178123
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 0ebf1e8a418..b48305e9cf4 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -134,7 +134,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::FP);
Reserved.set(PPC::FP8);
- Reserved.set(PPC::R0);
Reserved.set(PPC::R1);
Reserved.set(PPC::LR);
Reserved.set(PPC::LR8);
@@ -150,7 +149,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
if (Subtarget.isPPC64()) {
Reserved.set(PPC::R13);
- Reserved.set(PPC::X0);
Reserved.set(PPC::X1);
Reserved.set(PPC::X13);
OpenPOWER on IntegriCloud