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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 06:52:27 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-27 06:52:27 +0000 |
| commit | 0f77861d9f25c8d5212a2cee7729a6c6e448864d (patch) | |
| tree | 5ca2d97841cfd647adf47e7e09e1b783df1ee7b9 | |
| parent | 953c701b8b96aad1078cee68df377f47ebfb61d5 (diff) | |
| download | bcm5719-llvm-0f77861d9f25c8d5212a2cee7729a6c6e448864d.tar.gz bcm5719-llvm-0f77861d9f25c8d5212a2cee7729a6c6e448864d.zip | |
Allocate r0 on PPC
The R0 register can now be allocated because instructions
that cannot use R0 as a GPR have been appropriately marked.
llvm-svn: 178123
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/allocate-r0.ll | 18 |
2 files changed, 18 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 0ebf1e8a418..b48305e9cf4 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -134,7 +134,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(PPC::FP); Reserved.set(PPC::FP8); - Reserved.set(PPC::R0); Reserved.set(PPC::R1); Reserved.set(PPC::LR); Reserved.set(PPC::LR8); @@ -150,7 +149,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { if (Subtarget.isPPC64()) { Reserved.set(PPC::R13); - Reserved.set(PPC::X0); Reserved.set(PPC::X1); Reserved.set(PPC::X13); diff --git a/llvm/test/CodeGen/PowerPC/allocate-r0.ll b/llvm/test/CodeGen/PowerPC/allocate-r0.ll new file mode 100644 index 00000000000..1cf4cec0769 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/allocate-r0.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(i64 %a) nounwind { +entry: + call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind + br label %return + +; CHECK: @foo +; Because r0 is allocatable, we can use it to hold r3 without spilling. +; CHECK: mr 0, 3 +; CHECK: mr 3, 0 + +return: ; preds = %entry + ret i64 %a +} + |
