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authorAna Pazos <apazos@codeaurora.org>2018-10-11 22:49:13 +0000
committerAna Pazos <apazos@codeaurora.org>2018-10-11 22:49:13 +0000
commit0a5fcefa31bad39e7473a034c5ec3b4ed0c7f439 (patch)
tree668d04e8db5d33934593af96492d0a3e7a28bdbd /llvm/lib/Target
parentdfd1760b5f09470175638cc97ae033e750b92703 (diff)
downloadbcm5719-llvm-0a5fcefa31bad39e7473a034c5ec3b4ed0c7f439.tar.gz
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[RISCV] Fix disassembling of fence instruction with invalid field
Summary: Instruction with 0 in fence field being disassembled as fence , iorw. Printing "unknown" to match GAS behavior. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51828 llvm-svn: 344309
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
index aa21cf0e6b4..979c8f4e2fa 100644
--- a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -93,6 +93,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned FenceArg = MI->getOperand(OpNo).getImm();
+ assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
+
if ((FenceArg & RISCVFenceField::I) != 0)
O << 'i';
if ((FenceArg & RISCVFenceField::O) != 0)
@@ -101,6 +103,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
O << 'r';
if ((FenceArg & RISCVFenceField::W) != 0)
O << 'w';
+ if (FenceArg == 0)
+ O << "unknown";
}
void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
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