diff options
| author | Ana Pazos <apazos@codeaurora.org> | 2018-10-11 22:49:13 +0000 |
|---|---|---|
| committer | Ana Pazos <apazos@codeaurora.org> | 2018-10-11 22:49:13 +0000 |
| commit | 0a5fcefa31bad39e7473a034c5ec3b4ed0c7f439 (patch) | |
| tree | 668d04e8db5d33934593af96492d0a3e7a28bdbd /llvm | |
| parent | dfd1760b5f09470175638cc97ae033e750b92703 (diff) | |
| download | bcm5719-llvm-0a5fcefa31bad39e7473a034c5ec3b4ed0c7f439.tar.gz bcm5719-llvm-0a5fcefa31bad39e7473a034c5ec3b4ed0c7f439.zip | |
[RISCV] Fix disassembling of fence instruction with invalid field
Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.
This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.
Reviewers: asb
Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51828
llvm-svn: 344309
Diffstat (limited to 'llvm')
| -rw-r--r-- | llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt | 9 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32i-invalid.s | 1 |
3 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp index aa21cf0e6b4..979c8f4e2fa 100644 --- a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp @@ -93,6 +93,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned FenceArg = MI->getOperand(OpNo).getImm(); + assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); + if ((FenceArg & RISCVFenceField::I) != 0) O << 'i'; if ((FenceArg & RISCVFenceField::O) != 0) @@ -101,6 +103,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, O << 'r'; if ((FenceArg & RISCVFenceField::W) != 0) O << 'w'; + if (FenceArg == 0) + O << "unknown"; } void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, diff --git a/llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt b/llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt new file mode 100644 index 00000000000..5b20994dcb6 --- /dev/null +++ b/llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc -disassemble -triple=riscv32 < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -disassemble -triple=riscv64 < %s 2>&1 | FileCheck %s +# +# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer +# for the RISC-V assembly language. + +# This decodes as fence , iorw with invalid fence field as 0. +[0x0f 0x00 0xf0 0x00] +# CHECK: fence unknown, iorw diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index 92b9b4ad34f..f856bf1f934 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -6,6 +6,7 @@ fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letter fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw' fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' +fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' ## uimm5 slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] |
