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authorCraig Topper <craig.topper@intel.com>2018-10-03 20:28:43 +0000
committerCraig Topper <craig.topper@intel.com>2018-10-03 20:28:43 +0000
commitc39dc41b6348fed5534103a89af6c2547b95abc5 (patch)
treeccf3981c56f224e1ccd166d96c08cc20b9e80317 /llvm/lib/Target/X86
parentce9049952fa253791397028e88f3bcad3a7b87e6 (diff)
downloadbcm5719-llvm-c39dc41b6348fed5534103a89af6c2547b95abc5.tar.gz
bcm5719-llvm-c39dc41b6348fed5534103a89af6c2547b95abc5.zip
[X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1 SELECT into v8i1.
llvm-svn: 343713
Diffstat (limited to 'llvm/lib/Target/X86')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp14
-rw-r--r--llvm/lib/Target/X86/X86InstrCompiler.td2
2 files changed, 6 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cb79484d26e..88c7c0725e0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -19343,16 +19343,6 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
}
- if (VT == MVT::v4i1 || VT == MVT::v2i1) {
- SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
- Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
- DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
- Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
- DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
- SDValue newSelect = DAG.getSelect(DL, MVT::v8i1, Cond, Op1, Op2);
- return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
- }
-
if (Cond.getOpcode() == ISD::SETCC) {
if (SDValue NewCond = LowerSETCC(Cond, DAG)) {
Cond = NewCond;
@@ -27468,6 +27458,8 @@ static bool isCMOVPseudo(MachineInstr &MI) {
case X86::CMOV_VR256:
case X86::CMOV_VR256X:
case X86::CMOV_VR512:
+ case X86::CMOV_VK2:
+ case X86::CMOV_VK4:
case X86::CMOV_VK8:
case X86::CMOV_VK16:
case X86::CMOV_VK32:
@@ -29066,6 +29058,8 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case X86::CMOV_VR256:
case X86::CMOV_VR256X:
case X86::CMOV_VR512:
+ case X86::CMOV_VK2:
+ case X86::CMOV_VK4:
case X86::CMOV_VK8:
case X86::CMOV_VK16:
case X86::CMOV_VK32:
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 8b6d31cba50..379ed2822bf 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -599,6 +599,8 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
defm _VR256X : CMOVrr_PSEUDO<VR256X, v4i64>;
}
defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>;
+ defm _VK2 : CMOVrr_PSEUDO<VK2, v2i1>;
+ defm _VK4 : CMOVrr_PSEUDO<VK4, v4i1>;
defm _VK8 : CMOVrr_PSEUDO<VK8, v8i1>;
defm _VK16 : CMOVrr_PSEUDO<VK16, v16i1>;
defm _VK32 : CMOVrr_PSEUDO<VK32, v32i1>;
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