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| author | Mohammed Agabaria <mohammed.agabaria@intel.com> | 2017-01-25 09:14:48 +0000 |
|---|---|---|
| committer | Mohammed Agabaria <mohammed.agabaria@intel.com> | 2017-01-25 09:14:48 +0000 |
| commit | 20caee95e1aacb604ed1f7f946debeb58b793c8e (patch) | |
| tree | a09a902e16c75c93f5d5694d3a0fbf9261a7f6d4 /llvm/lib/Target/X86/X86TargetTransformInfo.cpp | |
| parent | bc934524206e8df60b0a05ef3f9b17b180594da4 (diff) | |
| download | bcm5719-llvm-20caee95e1aacb604ed1f7f946debeb58b793c8e.tar.gz bcm5719-llvm-20caee95e1aacb604ed1f7f946debeb58b793c8e.zip | |
[X86] enable memory interleaving for X86\SLM arch.
Differential Revision: https://reviews.llvm.org/D28547
llvm-svn: 293040
Diffstat (limited to 'llvm/lib/Target/X86/X86TargetTransformInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 073584870bb..bd7fa9ca617 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -2147,7 +2147,7 @@ bool X86TTIImpl::enableInterleavedAccessVectorization() { // TODO: We expect this to be beneficial regardless of arch, // but there are currently some unexplained performance artifacts on Atom. // As a temporary solution, disable on Atom. - return !(ST->isAtom() || ST->isSLM()); + return !(ST->isAtom()); } // Get estimation for interleaved load/store operations and strided load. |
