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| author | JF Bastien <jfb@google.com> | 2015-07-01 23:41:25 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2015-07-01 23:41:25 +0000 |
| commit | 03855df197944840745afd1180ebf423c7050c3c (patch) | |
| tree | 10279e6f356ea28fbb0e58df4b3eb958e1471b7a /llvm/lib/Target/WebAssembly/WebAssembly.td | |
| parent | 14cd13c51313e3a53a403eeb32b091d9c6a3011c (diff) | |
| download | bcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.tar.gz bcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.zip | |
WebAssembly: start instructions
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.
Test Plan: ninja check
Reviewers: sunfish
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D10880
llvm-svn: 241211
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssembly.td')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssembly.td | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td index f5e2564b165..a123bf6f66b 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.td +++ b/llvm/lib/Target/WebAssembly/WebAssembly.td @@ -22,8 +22,8 @@ include "llvm/Target/Target.td" // WebAssembly Subtarget features. //===----------------------------------------------------------------------===// -def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true", - "Enable SIMD">; +def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false", + "Enable 128-bit SIMD">; //===----------------------------------------------------------------------===// // Architectures. @@ -47,7 +47,11 @@ def WebAssemblyInstrInfo : InstrInfo; // WebAssembly Processors supported. //===----------------------------------------------------------------------===// -def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>; +// Minimal Viable Product. +def : ProcessorModel<"mvp", NoSchedModel, []>; + +// Latest and greatest experimental version of WebAssembly. Bugs included! +def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>; //===----------------------------------------------------------------------===// // Target Declaration |
