From 03855df197944840745afd1180ebf423c7050c3c Mon Sep 17 00:00:00 2001
From: JF Bastien <jfb@google.com>
Date: Wed, 1 Jul 2015 23:41:25 +0000
Subject: WebAssembly: start instructions

Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

llvm-svn: 241211
---
 llvm/lib/Target/WebAssembly/WebAssembly.td | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'llvm/lib/Target/WebAssembly/WebAssembly.td')

diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td
index f5e2564b165..a123bf6f66b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.td
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -22,8 +22,8 @@ include "llvm/Target/Target.td"
 // WebAssembly Subtarget features.
 //===----------------------------------------------------------------------===//
 
-def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
-                                   "Enable SIMD">;
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
+                                      "Enable 128-bit SIMD">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
@@ -47,7 +47,11 @@ def WebAssemblyInstrInfo : InstrInfo;
 // WebAssembly Processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
 
 //===----------------------------------------------------------------------===//
 // Target Declaration
-- 
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