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-rw-r--r--llvm/lib/Target/WebAssembly/WebAssembly.td10
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td
index f5e2564b165..a123bf6f66b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.td
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -22,8 +22,8 @@ include "llvm/Target/Target.td"
// WebAssembly Subtarget features.
//===----------------------------------------------------------------------===//
-def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
- "Enable SIMD">;
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
+ "Enable 128-bit SIMD">;
//===----------------------------------------------------------------------===//
// Architectures.
@@ -47,7 +47,11 @@ def WebAssemblyInstrInfo : InstrInfo;
// WebAssembly Processors supported.
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
//===----------------------------------------------------------------------===//
// Target Declaration
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