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| author | Daniel Cederman <cederman@gaisler.com> | 2018-04-20 07:47:12 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2018-04-20 07:47:12 +0000 |
| commit | c67b3ffba743e8de1c46b5363bf9801e20da5744 (patch) | |
| tree | 979ecf1dd7213bd074d3e34bbe66ceca783ac2a8 /llvm/lib/Target/Sparc | |
| parent | 2473183c15a2396a307c6f8fdc921608185a8a5a (diff) | |
| download | bcm5719-llvm-c67b3ffba743e8de1c46b5363bf9801e20da5744.tar.gz bcm5719-llvm-c67b3ffba743e8de1c46b5363bf9801e20da5744.zip | |
[Sparc] Use synthetic instruction clr to zero register instead of sethi
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D45810
llvm-svn: 330396
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 08bccbde0bd..ad00c83171d 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1599,6 +1599,9 @@ let Predicates = [HasV9] in { // Non-Instruction Patterns //===----------------------------------------------------------------------===// +// Zero immediate. +def : Pat<(i32 0), + (ORrr (i32 G0), (i32 G0))>; // Small immediates. def : Pat<(i32 simm13:$val), (ORri (i32 G0), imm:$val)>; |
