[Sparc] Use synthetic instruction clr to zero register instead of sethi

Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45810

llvm-svn: 330396

5 files changed, 54 insertions, 4 deletions

diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 08bccbde0bd..ad00c83171d 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -1599,6 +1599,9 @@ let Predicates = [HasV9] in {
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
+// Zero immediate.
+def : Pat<(i32 0),
+          (ORrr (i32 G0), (i32 G0))>;
 // Small immediates.
 def : Pat<(i32 simm13:$val),
           (ORri (i32 G0), imm:$val)>;
diff --git a/llvm/test/CodeGen/SPARC/atomics.ll b/llvm/test/CodeGen/SPARC/atomics.ll
index ac095e60fa0..17aa227ec9a 100644
--- a/llvm/test/CodeGen/SPARC/atomics.ll
+++ b/llvm/test/CodeGen/SPARC/atomics.ll
@@ -82,7 +82,7 @@ entry:
 ; CHECK:       and %o0, 255, %o0
 ; CHECK:       sll %o0, %o1, %o0
 ; CHECK:       andn %g2, %o5, %g2
-; CHECK:       sethi 0, %o5
+; CHECK:       mov %g0, %o5
 ; CHECK:      [[LABEL1:\.L.*]]:
 ; CHECK:       or %g2, %o4, %g3
 ; CHECK:       or %g2, %o0, %g4
@@ -123,7 +123,7 @@ entry:
 ; CHECK:       sll %o0, %o1, %o0
 ; CHECK:       sll %o4, %o1, %o4
 ; CHECK:       andn %g2, %o5, %g2
-; CHECK:       sethi 0, %o5
+; CHECK:       mov %g0, %o5
 ; CHECK:      [[LABEL1:\.L.*]]:
 ; CHECK:       or %g2, %o0, %g3
 ; CHECK:       or %g2, %o4, %g4
@@ -235,6 +235,7 @@ entry:
 
 ; CHECK-LABEL: test_load_add_i32
 ; CHECK: membar
+; CHECK: mov %g0
 ; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
 ; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
 ; CHECK: cas [%o0], [[V]], [[V2]]
diff --git a/llvm/test/CodeGen/SPARC/imm.ll b/llvm/test/CodeGen/SPARC/imm.ll
new file mode 100644
index 00000000000..a1afb56c9a3
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/imm.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=sparc | FileCheck %s -check-prefix=SPARC
+
+; Materializing constants
+
+define i32 @zero() nounwind {
+; SPARC-LABEL: zero:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov %g0, %o0
+ret i32 0
+}
+
+define i32 @pos_small() nounwind {
+; SPARC-LABEL: pos_small:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov 2047, %o0
+  ret i32 2047
+}
+
+define i32 @neg_small() nounwind {
+; SPARC-LABEL: neg_small:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    mov -2047, %o0
+  ret i32 -2047
+}
+
+define i32 @pos_i32() nounwind {
+; SPARC-LABEL: pos_i32:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    sethi 1695242, %o0
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    or %o0, 751, %o0
+  ret i32 1735928559
+}
+
+define i32 @neg_i32() nounwind {
+; SPARC-LABEL: neg_i32:
+; SPARC:       ! %bb.0:
+; SPARC-NEXT:    sethi 3648367, %o0
+; SPARC-NEXT:    retl
+; SPARC-NEXT:    or %o0, 751, %o0
+  ret i32 -559038737
+}
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll
index d4584f8d230..7bf0f74d948 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -84,7 +84,7 @@ attributes #0 = { "no-frame-pointer-elim"="true" }
 
 ;; Ensures that tied in and out gets allocated properly.
 ; CHECK-LABEL: test_i64_inout:
-; CHECK: sethi 0, %o2
+; CHECK: mov %g0, %o2
 ; CHECK: mov 5, %o3
 ; CHECK: xor %o2, %g0, %o2
 ; CHECK: mov %o2, %o0
diff --git a/llvm/test/CodeGen/SPARC/vector-extract-elt.ll b/llvm/test/CodeGen/SPARC/vector-extract-elt.ll
index 9a5ac6920c6..b76e0e9c15e 100644
--- a/llvm/test/CodeGen/SPARC/vector-extract-elt.ll
+++ b/llvm/test/CodeGen/SPARC/vector-extract-elt.ll
@@ -7,7 +7,7 @@
 define i1 @test1(<4 x i16>* %in) {
 ; CHECK-LABEL: ! %bb.0:
 ; CHECK-NEXT:        retl
-; CHECK-NEXT:        sethi 0, %o0
+; CHECK-NEXT:        mov %g0, %o0
   %vec2 = load <4 x i16>, <4 x i16>* %in, align 1
   %vec3 = lshr <4 x i16> %vec2, <i16 2, i16 2, i16 2, i16 2>
   %vec4 = sext <4 x i16> %vec3 to <4 x i32>