From 15e894baeeb96612ae471fa83d1729a2d3388fc8 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Thu, 26 Apr 2018 14:04:18 +0000 Subject: [RISCV] Implement isZextFree This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected and avoiding unnecessary masks. llvm-svn: 330943 --- llvm/lib/Target/RISCV/RISCVISelLowering.h | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.h') diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 2a2016ef5f5..83a3bfdda4d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -46,6 +46,7 @@ public: bool isLegalAddImmediate(int64_t Imm) const override; bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; + bool isZExtFree(SDValue Val, EVT VT2) const override; // Provide custom lowering hooks for some operations. SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; -- cgit v1.2.3