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authorAlex Bradbury <asb@lowrisc.org>2017-12-13 09:57:25 +0000
committerAlex Bradbury <asb@lowrisc.org>2017-12-13 09:57:25 +0000
commit19c9314aea1634800974de2199a1bdab0a63c7ea (patch)
tree4e6ce6e0c2a6a6f47e567f377ef956ec6514c454 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
parent581d6b081debcd8496de2c796d1e25014b9dc13a (diff)
downloadbcm5719-llvm-19c9314aea1634800974de2199a1bdab0a63c7ea.tar.gz
bcm5719-llvm-19c9314aea1634800974de2199a1bdab0a63c7ea.zip
[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction with a _ in that place. e.g. fadd.s -> FADD_S. This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP. Also includes some minor formatting changes in RISCVInstrInfoC.td to better align it with the formatting conventions in the rest of the backend. llvm-svn: 320560
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
-rw-r--r--llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp14
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 932bc710508..563edc9e29d 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -186,14 +186,16 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
// Add implied SP operand for instructions *SP compressed instructions. The SP
// operand isn't explicitly encoded in the instruction.
static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
- if (Inst.getOpcode() == RISCV::CLWSP || Inst.getOpcode() == RISCV::CSWSP ||
- Inst.getOpcode() == RISCV::CLDSP || Inst.getOpcode() == RISCV::CSDSP ||
- Inst.getOpcode() == RISCV::CFLWSP || Inst.getOpcode() == RISCV::CFSWSP ||
- Inst.getOpcode() == RISCV::CFLDSP || Inst.getOpcode() == RISCV::CFSDSP ||
- Inst.getOpcode() == RISCV::CADDI4SPN) {
+ if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
+ Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
+ Inst.getOpcode() == RISCV::C_FLWSP ||
+ Inst.getOpcode() == RISCV::C_FSWSP ||
+ Inst.getOpcode() == RISCV::C_FLDSP ||
+ Inst.getOpcode() == RISCV::C_FSDSP ||
+ Inst.getOpcode() == RISCV::C_ADDI4SPN) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}
- if (Inst.getOpcode() == RISCV::CADDI16SP) {
+ if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}
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