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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-21 14:32:39 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-21 14:32:39 +0000 |
commit | af1ab22a768f97d9cb585886e157f2c948819f4d (patch) | |
tree | 5ba92d231639023c0c3f597344915be96d1a4138 /llvm/lib/Target/PowerPC/PPCISelLowering.cpp | |
parent | 57733507fea37e84c1b0eb4d9f7ef0a8498d60b2 (diff) | |
download | bcm5719-llvm-af1ab22a768f97d9cb585886e157f2c948819f4d.tar.gz bcm5719-llvm-af1ab22a768f97d9cb585886e157f2c948819f4d.zip |
[PPC] Always use the version of computeKnownBits that returns a value. NFCI.
Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version.
llvm-svn: 349903
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 92af82dc4b9..a1c2e2f74ee 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2216,11 +2216,10 @@ bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, // If this is an or of disjoint bitfields, we can codegen this as an add // (for better address arithmetic) if the LHS and RHS of the OR are provably // disjoint. - KnownBits LHSKnown, RHSKnown; - DAG.computeKnownBits(N.getOperand(0), LHSKnown); + KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0)); if (LHSKnown.Zero.getBoolValue()) { - DAG.computeKnownBits(N.getOperand(1), RHSKnown); + KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1)); // If all of the bits are known zero on the LHS or RHS, the add won't // carry. if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) { @@ -2319,8 +2318,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, // If this is an or of disjoint bitfields, we can codegen this as an add // (for better address arithmetic) if the LHS and RHS of the OR are // provably disjoint. - KnownBits LHSKnown; - DAG.computeKnownBits(N.getOperand(0), LHSKnown); + KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0)); if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't @@ -11316,9 +11314,8 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N, } else { // This is neither a signed nor an unsigned comparison, just make sure // that the high bits are equal. - KnownBits Op1Known, Op2Known; - DAG.computeKnownBits(N->getOperand(0), Op1Known); - DAG.computeKnownBits(N->getOperand(1), Op2Known); + KnownBits Op1Known = DAG.computeKnownBits(N->getOperand(0)); + KnownBits Op2Known = DAG.computeKnownBits(N->getOperand(1)); // We don't really care about what is known about the first bit (if // anything), so clear it in all masks prior to comparing them. |