diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 13 |
2 files changed, 9 insertions, 15 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 4f05f50f699..2036dbd5460 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -688,9 +688,8 @@ bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) { SDValue Op1 = N->getOperand(1); SDLoc dl(N); - KnownBits LKnown, RKnown; - CurDAG->computeKnownBits(Op0, LKnown); - CurDAG->computeKnownBits(Op1, RKnown); + KnownBits LKnown = CurDAG->computeKnownBits(Op0); + KnownBits RKnown = CurDAG->computeKnownBits(Op1); unsigned TargetMask = LKnown.Zero.getZExtValue(); unsigned InsertMask = RKnown.Zero.getZExtValue(); @@ -734,8 +733,7 @@ bool PPCDAGToDAGISel::tryBitfieldInsert(SDNode *N) { // The AND mask might not be a constant, and we need to make sure that // if we're going to fold the masking with the insert, all bits not // know to be zero in the mask are known to be one. - KnownBits MKnown; - CurDAG->computeKnownBits(Op1.getOperand(1), MKnown); + KnownBits MKnown = CurDAG->computeKnownBits(Op1.getOperand(1)); bool CanFoldMask = InsertMask == MKnown.One.getZExtValue(); unsigned SHOpc = Op1.getOperand(0).getOpcode(); @@ -4613,8 +4611,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) { int16_t Imm; if (N->getOperand(0)->getOpcode() == ISD::FrameIndex && isIntS16Immediate(N->getOperand(1), Imm)) { - KnownBits LHSKnown; - CurDAG->computeKnownBits(N->getOperand(0), LHSKnown); + KnownBits LHSKnown = CurDAG->computeKnownBits(N->getOperand(0)); // If this is equivalent to an add, then we can fold it with the // FrameIndex calculation. diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 92af82dc4b9..a1c2e2f74ee 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2216,11 +2216,10 @@ bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, // If this is an or of disjoint bitfields, we can codegen this as an add // (for better address arithmetic) if the LHS and RHS of the OR are provably // disjoint. - KnownBits LHSKnown, RHSKnown; - DAG.computeKnownBits(N.getOperand(0), LHSKnown); + KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0)); if (LHSKnown.Zero.getBoolValue()) { - DAG.computeKnownBits(N.getOperand(1), RHSKnown); + KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1)); // If all of the bits are known zero on the LHS or RHS, the add won't // carry. if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) { @@ -2319,8 +2318,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, // If this is an or of disjoint bitfields, we can codegen this as an add // (for better address arithmetic) if the LHS and RHS of the OR are // provably disjoint. - KnownBits LHSKnown; - DAG.computeKnownBits(N.getOperand(0), LHSKnown); + KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0)); if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't @@ -11316,9 +11314,8 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N, } else { // This is neither a signed nor an unsigned comparison, just make sure // that the high bits are equal. - KnownBits Op1Known, Op2Known; - DAG.computeKnownBits(N->getOperand(0), Op1Known); - DAG.computeKnownBits(N->getOperand(1), Op2Known); + KnownBits Op1Known = DAG.computeKnownBits(N->getOperand(0)); + KnownBits Op2Known = DAG.computeKnownBits(N->getOperand(1)); // We don't really care about what is known about the first bit (if // anything), so clear it in all masks prior to comparing them. |
