- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo

  and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884

1 files changed, 1 insertions, 1 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
index 3ce96b81a94..51fa1ea1b57 100644
--- a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -70,7 +70,7 @@ bool SPUSubtarget::enablePostRAScheduler(
 MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
                                           StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
-  InitSPUMCSubtargetInfo(X, CPU, FS);
+  InitSPUMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }