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authorEvan Cheng <evan.cheng@apple.com>2011-07-11 03:57:24 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-07-11 03:57:24 +0000
commitc5e6d2f519b7f196fa3523c204977e7def9d0ded (patch)
treed3bc81d10d24f117b52bf298cbd2368714db1373 /llvm/lib/Target/CellSPU
parent403256763fc91a616a517a0ba0b128d28b8e166f (diff)
downloadbcm5719-llvm-c5e6d2f519b7f196fa3523c204977e7def9d0ded.tar.gz
bcm5719-llvm-c5e6d2f519b7f196fa3523c204977e7def9d0ded.zip
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
Diffstat (limited to 'llvm/lib/Target/CellSPU')
-rw-r--r--llvm/lib/Target/CellSPU/SPUInstrInfo.cpp13
-rw-r--r--llvm/lib/Target/CellSPU/SPUSubtarget.cpp2
2 files changed, 13 insertions, 2 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
index 93b6d4c5569..12fae9df878 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -17,10 +17,11 @@
#include "SPUTargetMachine.h"
#include "SPUHazardRecognizers.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/Target/TargetRegistry.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/MC/MCContext.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
@@ -450,3 +451,13 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
return true;
}
+
+MCInstrInfo *createSPUMCInstrInfo() {
+ MCInstrInfo *X = new MCInstrInfo();
+ InitSPUMCInstrInfo(X);
+ return X;
+}
+
+extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
+ TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
+}
diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
index 3ce96b81a94..51fa1ea1b57 100644
--- a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp
@@ -70,7 +70,7 @@ bool SPUSubtarget::enablePostRAScheduler(
MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
- InitSPUMCSubtargetInfo(X, CPU, FS);
+ InitSPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
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